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TMS 9900 Family System Development Manual
Company:
Texas Instruments
Part:
MP702
Date:
1977
Keywords:
Copies
No copies known to be online.
Table of Contents
Section I
Introduction
Section II
TMS 9900 Architecture
2.1
Registers
2.1.1
Workspace Pointer
2.1.2
Workspace Registers
2.1.3
Program Counter
2.1.4
Status Register
2.2
Memory-to-Memory Operations
2.3
Bus Structures
2.4
Context Switching
2.5
Machine Cycles
2.5.1
ALU Machine Cycles
2.5.2
Memory Read Machine Cycles
2.5.3
Memory Write Machine Cycles
2.5.4
CRU Output Machine Cycles
2.5.5
CRU Input Machine Cycles
2.5.6
Instruction Execution Examples
2.6
Machine Cycle Limits
Section III
Memory
3.1
Memory Organization
3.1.1
RESET Vector
3.1.2
Interrupt Vectors
3.1.3
Software Trap Vectors
3.1.4
LOAD Vector
3.1.5
Transfer Vectors Storage
3.2
Memory Control Signals
3.2.1
Memory Read Cycle
3.2.2
Memory Write Cycle
3.2.3
Read/Write Control with DBIN
3.2.4
Slow Memory Control
3.2.5
Wait State Control
3.2.6
Memory Access Time Calculation
3.3
Static Memory
3.3.1
Address
3.3.2
Control Signals
3.3.3
Loading
3.4
Dynamic Memory
3.4.1
Refresh
3.4.2
Refresh Modes
3.4.2.1
Block Refresh
3.4.2.2
Cycle Stealing
3.4.2.3
Transparent Refresh
3.5
Buffered Memory
3.6
Memory Parity
3.7
Direct Memory Access
3.8
Memory Layout
Section IV
Interrupts
4.1
RESET
4.2
LOAD
4.3
Maskable Interrupts
4.3.1
Interrupt Service
4.3.2
Interrupt Signals
4.3.3
Interrupt Masking
4.3.4
Interrupt Processing Example
Section V
Input/Output
5.1
Direct Memory Access
5.2
Memory Mapped I/O
5.3
Communication Register Unit (CRU)
5.3.1
CRU Interface
5.3.2
CRU Machine Cycles
5.3.2.1
CRU Output Machine Cycles
5.3.2.2
CRU Input Machine Cycles
5.3.3
CRU Data Transfer
5.3.3.1
Single Bit Instructions
5.3.3.2
LDCR Instruction
5.3.3.3
STCR Instruction
5.3.4
CRU Interface Logic
5.3.4.1
TTL Outputs
5.3.4.2
TTL Inputs
5.3.4.3
Expanding CRU I/O
5.4
CRU Paper Tape Reader Interface
5.4.1
Operation
5.4.2
Software Control
5.5
TMS 9902 Interface
5.5.1
Operation
5.5.2
Software Routines
5.6
Software -- UART
5.7
Burroughs SELF-SCAN Display Interface
5.8
Matrix Keyboard Interface
Section VI
Auxiliary System Functions
6.1
Unused Op Codes
6.1.1
Unused Op Code Detection
6.1.2
Unused Op Code Processing
6.2
Software Front Panel
6.2.1
System Configuration for Software Front Panel
6.2.2
Memory Requirements
6.2.3
Description of Operation
6.2.3.1
Entry Into Front-Panel Mode
6.2.3.2
Single Instruction Execution
6.2.3.3
Return to Run Mode
Section VII
Electrical Requirements
7.1
TMS 9900 Clock Generation
7.1.1
TIM 9904 Clock Generator
7.1.2
TTL Clock Generator
7.2
TMS 9900 Signal Interfacing
7.2.1
Switching Levels
7.2.2
Loading
7.2.3
Recommended Interface Logic
7.2.4
System Layout
Section VIII
TMS 9980A/81
8.1
Architecture
8.2
Memory
8.3
Interrupts
8.4
Input/Output
8.5
External Instructions
8.6
TMS 9980A/81 System Clock
Section IX
TMS 9900 Family Support Devices
Appendix A
TMS 9900 Family Machine Cycles
A.1
General Description of Machine Cycles
A.1.1
ALU Cycle
A.1.2
Memory Cycle
A.1.3
CRU Cycle
A.2
TMS 9900 Machine Cycle Sequences
A.3
Terms and Definitions
A.4
Data Derivation Sequences
A.4.1
Workspace Register
A.4.2
Workspace Register Indirect
A.4.3
Workspace Register Indirect Auto-Increment (Byte Operand)
A.4.4
Workspace Register Indirect Auto-Increment (Word Operand)
A.4.5
Symbolic
A.4.6
Indexed
A.5
Instruction Execution Sequences
A.5.1
A, AB, C, CB, S, SB, SOC, SOCB, SZC, SZCB, MOV, MOVB, COC, CZC, XOR
A.5.2
MPY (Multiply)
A.5.3
DIV (Divide)
A.5.4
XOP
A.5.5
CLR, SETO, INV, NEG, INC, INCT, DEC, DECT
A.5.6
ABS
A.5.7
X
A.5.8
B
A.5.9
BL
A.5.10
BLWP
A.5.11
LDCR
A.5.12
STCR
A.5.13
SBZ, SBO
A.5.14
TB
A.5.15
JEQ, JGT, JH, JHE, JL, JLE, JLT, JMP, JNC, JNE, JNO, JOC, JOP
A.5.16
SRA, SLA, SRL, SRC
A.5.17
AI, ANDI, ORI
A.5.18
CI
A.5.19
LI
A.5.20
LWPI
A.5.21
LIMI
A.5.22
STWP, STST
A.5.23
CKON, CKOF, LREX, RSET
A.5.24
IDLE
A.6
Machine-Cycle Sequences in Response to External Stimuli
A.6.1
RESET
A.6.2
LOAD
A.6.3
Interrupts