VAX-11/780 Data Path Description

Chapter 1 Data Path Specification
- 1.1 Arithmetic Section
  - 1.1.1 ALU
  - 1.1.2 AMX
  - 1.1.3 BMX
  - 1.1.4 SHF
  - 1.1.5 KMX
  - 1.1.6 MASK
  - 1.1.7 LC and RC
  - 1.1.8 LA and LB
  - 1.1.9 RLOG and PCSV
- 1.2 Exponent Section
  - 1.2.1 EALU
  - 1.2.2 EAMX
  - 1.2.3 EBMX
  - 1.2.4 FE
  - 1.2.5 STATE
  - 1.2.6 SMX
  - 1.2.7 SC
- 1.3 Data Section
  - 1.3.1 DFMX
    - 1.3.1.1 BUS DFMX
  - 1.3.2 QMX
  - 1.3.3 DMX
  - 1.3.4 DAL
  - 1.3.5 Q
  - 1.3.6 D
    - 1.3.6.1 MDBAL
  - 1.3.7 D PGEN
  - 1.3.8 BAL
  - 1.3.9 RAMX
    - 1.3.9.1 RBMX
- 1.4 Address Section
  - 1.4.1 VIBA
  - 1.4.2 VA
  - 1.4.3 VAMUX
  - 1.4.4 PC
  - 1.4.5 PCADD
  - 1.4.6 PCMX
Chapter 2 Micro Sequencer Specification
- 2.1 Normal Mode
- 2.2 Micro ECO Control (UECO) Mode
- 2.3 Micro Trap (UTRAP) Mode
- 2.4 Control Store Parity Error Micro Trap Mode
- 2.5 Cache Stalls
- 2.6 System Initialize
- 2.7 Micro Subroutine Field (USUB)
- 2.8 Jump Field (JFIELD or UJMP)
- 2.9 Branch Enable Field (UBEN)
- 2.10 Other Fields - UBS+UBCT (Not on USC)
- 2.11 Call Subroutine
- 2.12 Return Subroutine
- 2.13 Power Up or Down
- 2.14 Console Controlled Operations
- 2.15 Pico Sequencer and Priority Decoding
- 2.16 UPC Address Latching
Chapter 3 Internal Data Bus Specification
- 3.1 Functional Operation
  - 3.1.1 Normal Operation
    - 3.1.1.1 ID BUS Addresses
    - 3.1.1.2 ID BUS Directional Control
    - 3.1.1.3 ID BUS Data
    - 3.1.1.4 Signal Summary
    - 3.1.1.5 ID BUS Control
  - 3.1.2 Maintenance Operation
    - 3.1.2.1 Console Control of ID BUS
- 3.2 ID BUS Register Description
  - 3.2.1 IBUF DATA
  - 3.2.2 SYSTEM ID
  - 3.2.3 CNSL RXCS
  - 3.2.4 CNSL RXDB
  - 3.2.5 CNSL TXCS
  - 3.2.6 CNSL TXDB
  - 3.2.7 CLOCK CONTROL/STATUS
  - 3.2.8 NEXT INTERVAL COUNT
  - 3.2.9 INTERVAL COUNT
  - 3.2.10 TIME OF DAY
  - 3.2.11 ACC REG 0 THRU 1
  - 3.2.12 ACC MAINT
  - 3.2.13 ACC CONTROL/STATUS
  - 3.2.14 TBUF DATA
  - 3.2.15 TBUF REG0
  - 3.2.16 TBUF REG1
  - 3.2.17 SBI SILO
  - 3.2.18 SBI TIMEOUT ADDRESS
  - 3.2.19 SBI FAULT/STATUS
  - 3.2.20 SBI SILO COMPARATOR
  - 3.2.21 SBI MAINTENANCE
  - 3.2.22 SBI CACHE PARITY
  - 3.2.23 USTACK
  - 3.2.24 UBREAK
  - 3.2.25 WCS ADDRESS
  - 3.2.26 WCS DATA/STATUS
  - 3.2.27 D,Q (Maint Mode Only)
  - 3.2.28 SIR
  - 3.2.29 PSL
  - 3.2.30 CPU ERROR/STATUS
  - 3.2.31 VECTOR
  - 3.2.32 FPDA, D.SV, Q.SV
  - 3.2.33 P0BR, P1BR, SBR, P0LR, P1LR, SLR, PCBB, SCBB KSP, ESP, SSP, USP, ISP
Chapter 4 Instruction Buffer
- 4.1 Buffer Data Path
  - 4.1.1 Buffer Register
- 4.2 Shift Network
  - 4.2.1 Multiplexer Shift Network
    - 4.2.1.1 MICRO Control Use
- 4.3 Input Multiplexer
- 4.4 Byte Rotator
- 4.5 I-Stream Data Mux
- 4.6 PC Updates
- 4.7 IR Decode
  - 4.7.1 Register Latched Number
    - 4.7.1.1 Context Lookup
      - 4.7.1.1.1 Specifier 1 Constant
      - 4.7.1.1.2 Specifier 2 Constant
    - 4.7.1.2 Data Length Field
- 4.8 Execution Points
- 4.9 First Part Done
  - 4.9.1 IB Addressing
- 4.10 Cache Interface
- 4.11 Accelerator Interface
Chapter 5 Interrupts & Exceptions
- 5.1 Interrupts
  - 5.1.1 Interrupt Priority Level (IPL)
  - 5.1.2 System Control Block
  - 5.1.3 Vectors
  - 5.1.4 Interrupt Requests and their Vectors
  - 5.1.5 Description of Interrupt Conditions
    - 5.1.5.1 CPU Power Fail
    - 5.1.5.2 CPU Timeout
    - 5.1.5.3 SBI Fault
    - 5.1.5.4 SBI Alert
    - 5.1.5.5 CRD/RDS
    - 5.1.5.6 SBI SILO Compare
    - 5.1.5.7 Interval Timer
    - 5.1.5.8 External Device Interrupts
    - 5.1.5.9 Console Terminal Interrupts
    - 5.1.5.10 Software Interrupts
  - 5.1.6 UWORD Control for Interrupts
    - 5.1.6.1 Interrupt Strobe
    - 5.1.6.2 Interrupt Acknowledge
  - 5.1.7 Registers used for interrupt servicing
    - 5.1.7.1 Interrupt Priority Level Register - IPLR
    - 5.1.7.2 System Control Block Base Register - SCBB
    - 5.1.7.3 Vector Register, VECTOR
    - 5.1.7.4 Asynchronous System Trap Level Reg. ASTR
    - 5.1.7.5 Software Interrupt Summary Register SISR
    - 5.1.7.6 Software Interrupt Request Register SIRR
- 5.2 Exceptions
  - 5.2.1 Classes of Exceptions
    - 5.2.1.1 Traps
    - 5.2.1.2 Faults
    - 5.2.1.3 Aborts
  - 5.2.2 Exception conditions and their vectors
  - 5.2.3 Description of exception conditions
    - 5.2.3.1 Machine check - Raises IPL to 1F
      - 5.2.3.1.1 Read timeout
      - 5.2.3.1.2 Read data substitute
      - 5.2.3.1.3 Translation buffer parity error
      - 5.2.3.1.4 Cache parity error
      - 5.2.3.1.5 Control store parity error
      - 5.2.3.1.6 Illegal Machine Sequence Error
    - 5.2.3.2 Kernel stack not valid - Raises IPL to 1F
    - 5.2.3.3 Reserved DEC opcodes & priv. instr
    - 5.2.3.4 Reserved cust opcodes
    - 5.2.3.5 Reserved operands
      - 5.2.3.5.1 Illegal floating number - Fault
      - 5.2.3.5.2 Bit field too wide - Fault
      - 5.2.3.5.3 Illegal entry mask - Fault
      - 5.2.3.5.4 PSW MBZ FIELD not zero - Fault
      - 5.2.3.5.5 Illegal PCB entry - Abort
      - 5.2.3.5.6 Illegal PSL image - Fault
      - 5.2.3.5.7 Illegal processor reg - Fault
      - 5.2.3.5.8 Decimal string too long - Fault
      - 5.2.3.5.9 Reserved pattern operator - Fault
    - 5.2.3.6 Reserved addressing modes - Fault
    - 5.2.3.7 Access control violation - Fault
    - 5.2.3.8 Translation not valid - Fault
    - 5.2.3.9 Trace trap - TRAP
    - 5.2.3.10 BPT opcode - FAULT
    - 5.2.3.11 Compatibility mode trap - TRAP/ABORT
    - 5.2.3.12 Arithmetic trap - TRAP
    - 5.2.3.13 CHMX opcodes
  - 5.2.4 Acknowledging exceptions
    - 5.2.4.1 Error acknowledging
    - 5.2.4.2 Arithmetic trap acknowledging
    - 5.2.4.3 Trace trap acknowledging
    - 5.2.4.4 UWORD control for exceptions
- 5.3 Machine Halts
  - 5.3.1 Halt Conditions
    - 5.3.1.1 Halt Instruction
    - 5.3.1.2 CNSL Halt
    - 5.3.1.3 CHMX Instructions
    - 5.3.1.4 Interrupt Stack Not Valid
    - 5.3.1.5 Halt Code from Vector
- 5.4 UTRAP Function
  - 5.4.1 UTRAP Conditions and their Vectors
  - 5.4.2 Description of utrap conditions
    - 5.4.2.1 System Init
    - 5.4.2.2 Errors
    - 5.4.2.3 Reserved Floating Operand
    - 5.4.2.4 TBUF Miss
    - 5.4.2.5 Protection Violation
    - 5.4.2.6 MBIT
    - 5.4.2.7 Page Boundary
    - 5.4.2.8 Unaligned Data
- 5.5 Serialization of Events at Fork A
Chapter 6 Machine Check Abort/Fault/Halt
- 6.1 Machine Checks
- 6.2 Instruction Aborts
- 6.3 Instruction Faults
- 6.4 Instruction Halts
- 6.5 Error Logout
- 6.6 Initialization of CP, TBUF, CACHE, & SBI Status Registers
- 6.7 CPU/Console Interface State
- 6.8 Halt Identification Codes
- 6.9 Retryable Instruction List
Chapter 7 CACHE-SBI-TB Subsystem
- 7.1 MD Bus
- 7.2 CS Bus
- 7.3 V Bus
- 7.4 Clock Bus
- 7.5 Address Bus
- 7.6 From IB
- 7.7 To IB
- 7.8 From Microsequence
- 7.9 To Microsequencer
- 7.10 From Traps and Interrupts
- 7.11 To Traps and Interrupts
- 7.12 From Data Path - None
- 7.13 To Data Path
- 7.14 Selected Internal Subsystem Signals
- 7.15 Microbranches
- 7.16 Microorders
- 7.17 Registers
- 7.18 General Description
- 7.19 Microcoding Suggestions
Chapter 8 VAX 11/780 Console Subsystem
- 8.1 The Console/CPU Interface
- 8.2 ID Bus Registers on CIB
- 8.3 The Q-Bus Registers
- 8.4 Use of the Q-Bus Registers
- 8.5 Terminal Control Registers in the Procreg Space
Chapter 9 VAX 11/780 Accelerator Interface
- 9.1 Definitions
- 9.2 Interface Specification
- 9.3 Glossary of Interface Signals
- 9.4 Accelerator Interface Operation
  - 9.4.1 Data transfer
    - 9.4.1.1 Initial data transfer
  - 9.4.2 Accelerator control
    - 9.4.2.1 Accelerator trap
    - 9.4.2.2 Alternate trap function
    - 9.4.2.3 CPU branches
  - 9.4.3 System clock
- 9.5 Data Interface
  - 9.5.1 Data to accelerator
    - 9.5.1.1 Data from accelerator
  - 9.5.2 Alternate data transfers
  - 9.5.3 Accelerator status registers
    - 9.5.3.1 Accelerator maintenance register
  - 9.5.4 General register updates
- 9.6 ISB Interface
Appendix A Control Word
- A.1 The Control Word
- A.2 Abort Condition
Appendix B Writable Control Store
- B.1 Writable Control Store Memory
- B.2 Write Data to WCS
- B.3 WCS Address Register
- B.4 External Jumper Selections & RAM Type Selection
Appendix C Micro-Code Debuffer Interface
- C.1 Objectives
- C.2 Micro-Code Debugger Entry & Exit
- C.3 Micro-Code Debugger/Micro-Machine/State Control
- C.4 Micro-Code Debugger Internal Register & Memory Examine & Deposit
- C.5 List of Dependent Micro-Orders
Appendix D WCS Debugger Help File
Appendix E PROM Control Store Specification
- E.1 PROM Address Path
- E.2 Parity Error Detection
- E.3 External Jumper Selections & CS Type Selection

Company:	Digital Equipment Corporation
Part:	AA-H307A-TE
Date:	1979-02
Keywords:

Address:	http://bitsavers.org/pdf/dec/vax/780/AA-H307-TE_VAX-11_780_Data_Path_Description_197902.pdf
Site:	Al Kossow's Bitsavers
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VAX-11/780 Data Path Description

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