KD11-B Processor Maintenance Manual

Chapter 1 Introduction
- 1.1 Scope
- 1.2 Organization
Chapter 2 Microprogram Control
- 2.1 Introduction
- 2.2 Microprogrammed Versus Conventional Control
- 2.3 Control Store
- 2.4 Branching Within Microroutines
- 2.5 Microprogram Flow
  - 2.5.1 Flow Chart Notation
  - 2.5.2 Interrupts and Traps
  - 2.5.3 Console Functions
- 2.6 Microprogram Symbolic Listing
- 2.7 Microprogram Binary Listing
- 2.8 Microprogram Cross Reference Listing
Chapter 3 Console Description
- 3.1 Introduction
- 3.2 General Description
  - 3.2.1 ADDRESS/DATA Register Logic
  - 3.2.2 Control Switch Logic
- 3.3 Detailed Description
  - 3.3.1 Multiplexer
  - 3.3.2 Clock
  - 3.3.3 Counter
  - 3.3.4 Display Buffer and Driver
  - 3.3.5 Control Switches and Logic
    - 3.3.5.1 Normal Operating Mode
    - 3.3.5.2 Panel Lock Mode
    - 3.3.5.3 Power Loss During Operation
Chapter 4 KD11-B Detailed Description
- 4.1 Introduction
- 4.2 ROMs As Generalized Gates
- 4.3 KD11-B Data Path, Simplified Description
  - 4.3.1 Data Path (DP) Detailed Description
  - 4.3.2 DP Data Polarities
  - 4.3.3 Control Logic and Microprogramming (CON)
  - 4.3.4 A-Multiplexer
  - 4.3.5 Arithmetic Logic Unit (ALU)
  - 4.3.6 B Register
    - 4.3.6.1 Functional Description
    - 4.3.6.2 BLEG Operations That Provide Input to the ALU
    - 4.3.6.3 BREG Shifting Operations
  - 4.3.7 Byte Instructions
  - 4.3.8 Scratch Pad Memory
  - 4.3.9 Scratch Pad Memory Address Multiplexer
  - 4.3.10 Processor Status Word Register
  - 4.3.11 Constants Generator
  - 4.3.12 Console Switch Register
  - 4.3.13 Switch Register Multiplexers
  - 4.3.14 Console Multiplexer
- 4.4 Instruction Decoding
  - 4.4.1 Introduction
  - 4.4.2 Double Operand Instructions
  - 4.4.3 Branch On Unary
  - 4.4.4 PDP-11 Branch Instructions
  - 4.4.5 Operate Instructions
  - 4.4.6 Auxiliary ALU Control
- 4.5 Processor Clock
- 4.6 Unibus Control
  - 4.6.1 DATI Timing
  - 4.6.2 DATI Operation
    - 4.6.2.1 DATIP Operation
    - 4.6.2.2 DATIP Logic
  - 4.6.3 DATO
  - 4.6.4 Byte Operations
  - 4.6.5 Bus Errors
- 4.7 Internal Unibus Addresses
- 4.8 Bus Requests
- 4.9 Non-Processor Requests (NPR)
- 4.10 Serial Communications Line Description (SCL)
- 4.11 Baud Rate Adjustment
- 4.12 Line Clock
  - 4.12.1 Introduction
  - 4.12.2 Flag Control
  - 4.12.3 Interrupt Control
- 4.13 Power Fail
Chapter 5 KD11-B and Console Maintenance
- 5.1 Introduction
- 5.2 Diagnostics
- 5.3 Types of Failures
- 5.4 Suggested Equipment
- 5.5 Procedures
- 5.6 Adjustments
- 5.7 KD11-B Print Function Table
- 5.8 External Clock Inputs
- 5.9 KM11 Maintenance Panel
- 5.10 Using KM11 Maintenance Panel
- 5.11 Console Maintenance

Company:	Digital Equipment Corporation
Part:	DEC-11-HKDBB-A-D
Date:	1975-01
Keywords:	PDP-11/05/10 PDP-11/05S

Address:	https://vt100.net/mirror/hcps/hkdbbad.pdf
Site:	VT100.net
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Address:	http://wwcm.synology.me/pdf/DEC-11-HKDBB-A-D KD11-B Processor Maintenance Manual.pdf
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KD11-B Processor Maintenance Manual

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