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PDP-11 Bus Handbook 1979
| Company: | Digital Equipment Corporation |
| Part: | |
| Date: | 1979 |
| Keywords: | |
Table of Contents
- Part 1 Unibus Specification
- Introduction
- Unibus Description
- Architecture
- Unibus Transmission Medium
- Bus Terminator
- Bus Segment
- Bus Repeater
- Bus Master
- Bus Slave
- Bus Arbitrator
- Bus Request
- Bus Grant
- Processor
- Interrupt Fielding Processor
- Unibus Systems
- Signal Lines
- Priority Structure
- Address Space
- Latency
- Arrangement of Devices on the Unibus
- Expanding the Unibus System
- Protocol
- Types of Transactions
- Priority Arbitration Transactions
- Data Transfers
- Initialization
- Unibus Signal Details
- Unibus Sections and Signal Lines
- Signal Transmission
- Bus Transmission Delay
- Skew
- Deskew
- Types of Unibus Signal Lines
- Priority Arbitration Section
- Non-Processor Request (NPR)
- Non-Processor Grant (NPG)
- Bus Request (BR4, BR5, BR6, BR7)
- Bus Grant (BG4, BG5, BG6, BG7)
- Selection Acknowledged (SACK)
- Bus Busy (BBSY)
- Data Transfer Section
- Data Lines, D<15:00>
- Address Lines, A<17:00>
- Control Lines, C0, C1
- Master Sync (MSYN)
- Slave Sync (SSYN)
- Interrupt Request (INTR)
- Initialization Section
- Intialize (INIT)
- AC Low (AC LO)
- DC Low (DC LO)
- Unibus Protocols
- Definitions and Concepts
- Arbitration
- Centralized Arbitration
- Priority Arbitration
- Data Transfer (Bus Cycle)
- Transaction
- Protocol
- Unibus Operation Concepts
- Priority Protocol
- Bus Device Priority Levels
- Interrupt Fielding Processor CPU Priority Levels
- Grant
- Assertion
- Negation
- Priority Arbitration Example
- Priority Arbitration Transactions
- Notes on the Timing Diagrams
- NPR Arbitration Sequence
- BR Interrupt Arbitration Sequence
- Data Transfer Protocol
- Data-In Transaction (DATI or DATIP)
- Detailed Description, DATI and DATIP
- Data-Out Transaction (DATO or DATOB)
- Detailed Description, DATO and DATOB
- Read/Modify/Write Transactions (DATIP-DATO/B)
- Multiple Word Transfers
- Initialization Section
- Initialization (INIT)
- Processor Requirements
- Arbitrator Response
- Master/Slave Response
- Power-Up and Power-Down Sequences
- Unibus Interface Design Guidelines
- Preferred Interface Integrated Circuit (IC) Chips
- Unibus Transmitter (Driver)
- Unibus Receiver
- Bus Receiver and Transmitter Equivalent Circuits
- DC Bus Load
- Module Layout
- Backplanes
- Grounding
- Logic Design Guidelines for Unibus Interfaces
- Master Devices
- Unibus Control Logic
- Bus Request (BR) Device---One Vector
- Bus Request (BR) Device---Two Vectors
- Non-Processor Request (NPR) Device
- Unibus Configuration
- Definitions
- Unibus Segment
- Unibus Cable
- Unibus Element
- AC Unit Load
- DC Unit Load
- Lumped Load
- Bus Terminator
- Semi-Lumped Load
- Data-In Transactions
- DATIP Transactions
- Data-Out Transactions
- Parity Error Indications (PA, PB)
- Master Sync (MSYN)
- Slave Sync (SSYN)
- Interrupt Request (INTR)
- AC Bus Load
- DC Bus Load
- Unibus Configuration Rules
- Maximum Cable Length (Rule 1)
- Maximum DC Loading (Rule 2)
- Maximum AC Loading (Rule 3)
- Different Cable Lengths (Rule 4)
- Voltage Margin Tests (Rule 5)
- Unibus Hardware
- Unibus Cable (BC11A)
- M920 Unibus Jumper Module
- M9202 Unibus Jumper with Cable
- M930 Unibus Terminator Module
- M981 Internal Unibus Terminator Assembly
- Drivers, Receivers, and Transmitters
- Unibus Connector Block Pin Assignments
- Part 2 LSI-11 Bus Specification
- Introduction
- Master/Slave Relationships
- Data Transfer Bus Cycles
- Bus Cycle Protocol
- Device Addressing
- DATI
- DATO(B)
- DATIO(B)
- Parity Protocol
- Direct Memory Access
- Interrupts
- Device Priority
- Interrupt Protocol
- 4-Level Interrupt Configurations (LSI-11/23)
- Control Functions
- Memory Refresh
- Halt
- Initialization
- Power Status
- Power-Up/Down Protocol
- Bus Electrical Characteristics
- AC Load Definition
- DC Load Definition
- 120 Ohm LSI-11 Bus
- Bus Drivers
- Bus Receivers
- Bus Termination
- Bus Interconnecting Wiring
- Backplane Wiring
- Intra-Backplane Wiring
- Power and Ground
- System Configurations
- Rules for Configuring Single Backplane Systems
- Rules for Configuring Multiple Backplane Systems
- Power Supply Loading
- Appendix A MASSBUS
- Appendix B DECdataway
- Appendix C PCL-11