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MM11-E Core Memory Manual

Company:	Digital Equipment Corporation
Part:	DEC-11-HR3A-D
Date:	1970-08
Keywords:	PDP-11
Cited by:	DEC-11-HDBA-D, DB11-A Bus Repeater Manual

Copies

Address:	http://bitsavers.org/pdf/dec/pdp11/memory/MM11-E_CoreMemoryManual.pdf
Site:	Al Kossow's Bitsavers
Format:	PDF
Size:	3185372 bytes (3.0 MiB)

Table of Contents

Chapter 1 Introduction
- 1.1 Scope
- 1.2 Introduction
- 1.3 General Description
  - 1.3.1 Core Array
  - 1.3.2 Memory Control
  - 1.3.3 Address Selection
  - 1.3.4 Inhibit Drivers
  - 1.3.5 Sense Amplifiers
  - 1.3.6 Data Register
  - 1.3.7 Switches and Drivers
  - 1.3.8 Current Generator
  - 1.3.9 G103 Levels and Gates Module
- 1.4 Basic Memory Operations
  - 1.4.1 Data In (DATI) Cycle
  - 1.4.2 Data In, Pause (DATIP) Cycle
  - 1.4.3 Data Out (DATO) Cycle
  - 1.4.4 Data Out, Byte (DATOB) Cycle
Chapter 2 Theory of Operation
- 2.1 Introduction
- 2.2 Core Array
- 2.3 Memory Operation
- 2.4 X- and Y-Line Selection
- 2.5 Drivers and Switches
- 2.6 Current Generator
- 2.7 Control and Logic Timing
  - 2.7.1 General
  - 2.7.2 Device Selection
  - 2.7.3 X-Y Address Latching
  - 2.7.4 Data In (DATI) Control Circuits
  - 2.7.5 Data In, Pause (DATIP) Control Circuits
  - 2.7.6 Data Out (DATO) Control Circuits
  - 2.7.7 DATOB Control Circuits
- 2.8 Read Operation
- 2.9 Write Operation
Chapter 3 Maintenance
- 3.1 Introduction
- 3.2 Adjustments
  - 3.2.1 Equipment Required
  - 3.2.2 Initial Procedures
  - 3.2.3 Voltage Reference Adjustment
  - 3.2.4 Voltage Size Adjustment
  - 3.2.5 Strobe Adjustment
- 3.3 Maintenance
Chapter 4 MM11-E Engineering Drawings