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KE11-A Extended Arithmetic Element
| Company: | Digital Equipment Corporation |
| Part: | DEC-11-HKEA-D |
| Date: | 1971-05 |
| Keywords: | PDP-11 |
Table of Contents
- Chapter 1 General Description and Installation
- 1.1 General Description
- 1.2 Specifications
- 1.3 Documentation
- 1.4 Installation
- Chapter 2 Programming the KE11-A
- 2.1 KE11-A Registers
- 2.1.1 Multiplier Quotient Register
- 2.1.2 Accumulator Register
- 2.1.3 The Step Counter
- 2.1.4 The Status Register (SR)
- 2.1.5 The X Register
- 2.2 KE11-A Operations
- 2.2.1 Multiplication
- 2.2.2 Division
- 2.2.3 Normalization
- 2.2.4 Logical Shifts
- 2.2.5 Arithmetic Shift
- 2.3 PDP-11 Instructions and the KE11-A
- 2.3.1 Multiplication and Division
- 2.4 KE11-A Timing
- Chapter 3 Theory of Operation
- 3.1 Binary 2's Complement Notation
- 3.2 Multiplication
- 3.3 Division
- 3.4 Algorithms for KE11-A Operation
- 3.4.1 Basic Shift Operation
- 3.4.2 Multiplication
- 3.4.2.1 Multiply Algorithm
- 3.4.2.2 Multiplication Example
- 3.4.3 Division
- 3.4.3.1 Division Cycle
- 3.4.3.2 Overflow Detection
- 3.4.3.3 Remainder Correction
- 3.4.3.4 Division Register Structure
- 3.4.3.5 Division Algorithm
- 3.4.3.6 Division Example
- 3.4.4 Shift Operations
- Chapter 4 General Hardware Description
- 4.1 Block Division Discussion
- 4.2 Operation Cycles
- 4.2.1 Multiplication
- 4.2.1.1 Multiply Implementation
- 4.2.1.2 Multiplication Example
- 4.2.2 Division
- 4.2.2.1 Divide Implementation
- 4.2.2.2 Division Examples
- 4.2.3 Shifts
- Chapter 5 Detailed Hardware Description
- Chapter 6 Maintenance
- Appendix A Complex IC Descriptions
- A.1 7482 Adders
- A.2 74H87 4-Bit Sign Extender
- A.3 74153 4-Way Multiplexer
- A.4 8271 4-Bit Shift Register
- Appendix B KE11-A Instruction Summary
- Appendix C Names of Mathematical Terms