KB11-A Central Processor Unit Maintenance Manual

Chapter 1 General Description
- 1.1 System Description
  - 1.1.1 The Basic System
  - 1.1.2 A Faster Basic System
  - 1.1.3 A Virtual Machine System
  - 1.1.4 Expanded Systems
- 1.2 Functional Description
  - 1.2.1 Data Manipulation
  - 1.2.2 Transferring Data
  - 1.2.3 Handling Instructions
  - 1.2.4 Handling Asynchronous Conditions
Chapter 2 Address Modes and Instruction Set
- 2.1 Address Modes
- 2.2 KB11-A Instructions
Chapter 3 Operation
- 3.1 Console Controls and Indicators
- 3.2 Power On
  - 3.2.1 ENABL Function
  - 3.2.2 HALT Function
- 3.3 Console Operations
  - 3.3.1 HALT Switch Functions
    - 3.3.1.1 HALT/CONT with S INST
    - 3.3.1.2 HALT/CONT with S BUS CYCLE
  - 3.3.2 EXAM Switch Functions
  - 3.3.3 DEP Switch Functions
  - 3.3.4 REG EXAM and REG DEP Functions
- 3.4 Address Display Select
  - 3.4.1 PROG PHY Function
  - 3.4.2 CONS PHY Function
  - 3.4.3 USER, SUPER, or KERNEL Functions
- 3.5 How to Load and Run Programs
  - 3.5.1 Loading the PDP-11 Bootstrap Loader
  - 3.5.2 Loading the PDP-11 Absolute Binary Loader
  - 3.5.3 Loading the Maintenance Loader
Chapter 4 Principles of Operation
- 4.1 Microprogramming
  - 4.1.1 Digital Computer Description
  - 4.1.2 The Data Section
    - 4.1.2.1 The Data Storage Section
    - 4.1.2.2 The Data Manipulation Section
    - 4.1.2.3 The Data Routing Section
    - 4.1.2.4 The Data Section in the KB11-A
  - 4.1.3 The Control Section
    - 4.1.3.1 The Sequence Control Section
    - 4.1.3.2 The Function Generator
    - 4.1.3.3 The Sensing Logic
    - 4.1.3.4 The Control Section in the KB11-A
  - 4.1.4 Microprogramming in the Control Section Implementation
    - 4.1.4.1 Conventional Implementation
    - 4.1.4.2 Microprogrammed Implementation
- 4.2 Parallel Operation (Pipelining)
- 4.3 Virtual Machines
  - 4.3.1 Mapping
  - 4.3.2 Resource Management
    - 4.3.2.1 Processor Management
    - 4.3.2.2 Memory Management
    - 4.3.2.3 Memory Use Statistics
  - 4.3.3 Communication
    - 4.3.3.1 Context Switching
    - 4.3.3.2 Inter-Program Data Transfers
    - 4.3.3.3 Returning to the Previous Context
  - 4.3.4 Protection
    - 4.3.4.1 Separate Address Spaces
    - 4.3.4.2 Access Modes
    - 4.3.4.3 Privileged Instructions
- 4.4 Re-Entrant and Recursive Programming
  - 4.4.1 Recursive Functions
  - 4.4.2 Use of a Stack in Recursive Routines
  - 4.4.3 Re-Entrant Functions
  - 4.4.4 Indexed Addressing of Parameters
  - 4.4.5 Separate Stack and Index Pointers
  - 4.4.6 Subroutine Call Compatibility
  - 4.4.7 The MARK Instruction
- 4.5 Processor Status Operation
  - 4.5.1 Current Processor Mode
  - 4.5.2 Previous Processor Mode
  - 4.5.3 Register Set Selection
  - 4.5.4 Processor Priority
    - 4.5.4.1 Device Priorities
    - 4.5.4.2 Program Priorities
    - 4.5.4.3 Programmed Interrupt Requests
  - 4.5.5 The Trace Bit
  - 4.5.6 The Condition Codes
- 4.6 Stack Limit Protection
- 4.7 The Multiply and Divide Instructions
  - 4.7.1 Number Representation
  - 4.7.2 The Multiply Algorithm
  - 4.7.3 Sign Correction During Multiplication
  - 4.7.4 The Divide Instruction
Chapter 5 Block Diagram Description
- 5.1 Data Paths Block Diagram
- 5.2 General Storage Registers
  - 5.2.1 Program Counter (PC)
  - 5.2.2 Stack Pointers (SP)
  - 5.2.3 General Register Sets
- 5.3 Temporary Storage Registers
  - 5.3.1 Source Register (SR)
  - 5.3.2 Destination Register (DR)
  - 5.3.3 Bus Register (BR and BRA)
- 5.4 Special Purpose Registers
  - 5.4.1 Instruction Register (IR)
  - 5.4.2 Shift Counter (SC)
  - 5.4.3 Processor Status Register (PS)
  - 5.4.4 Programmed Interrupt Request Register (PIRQ)
  - 5.4.5 Stack Limit Register (SL)
  - 5.4.6 Microprogram Break Register (PB)
  - 5.4.7 Console Switches (SW) and Light Register (LR)
- 5.5 Data Manipulation
  - 5.5.1 Arithmetic and Logic Unit (ALU)
  - 5.5.2 Shifter (SHFR)
  - 5.5.3 Constant Multiplexers (K0MX, K1MX)
  - 5.5.4 Destination Register (DR)
  - 5.5.5 Shift Counter (SC)
- 5.6 Data Routing Elements
  - 5.6.1 ALU Interface Multiplexers
  - 5.6.2 Temporary Storage Register Input Multiplexers
  - 5.6.3 External Interface Multiplexers
- 5.7 Control Section
  - 5.7.1 ROM Microprogram Control
  - 5.7.2 External Interface Control
    - 5.7.2.1 Unibus and Console Control (UBC) Module
    - 5.7.2.2 Traps and Miscellaneous Control (TMC) Module
    - 5.7.2.3 The Timing Generator (TIG) Module
- 5.8 Special Control Logic
  - 5.8.1 Arithmetic and Logic Unit (ALU) Control
  - 5.8.2 Condition Code Control
  - 5.8.3 General Register Control
Chapter 6 Microprogram Flow Diagrams
- 6.1 How to Read the Flowcharts
  - 6.1.1 Machine State Description
  - 6.1.2 Machine State Information in the ROM Map
  - 6.1.3 Machine State Sequence Information
  - 6.1.4 Sequence Symbols in the Flowcharts
    - 6.1.4.1 Flow Lines
    - 6.1.4.2 Connector Symbols
    - 6.1.4.3 Branch Condition Symbols
  - 6.1.5 Locating a Machine State in the Flowcharts
- 6.2 Flowchart Organization
  - 6.2.1 Instruction Fetch
    - 6.2.1.1 The Fetch States
    - 6.2.1.2 Instruction Decoding
    - 6.2.1.3 Source Modes 1 through 5
    - 6.2.1.4 Move to Previous Space Instructions
    - 6.2.1.5 Branch Instructions
  - 6.2.2 Indexed Source Modes and Operate Instructions
    - 6.2.2.1 Indexed Source Modes
    - 6.2.2.2 Floating-Point Instructions
    - 6.2.2.3 RTI and RTT Instructions
    - 6.2.2.4 RTS Instruction
    - 6.2.2.5 SOB Instruction
    - 6.2.2.6 MARK Instruction
  - 6.2.3 No Memory Reference Execution
    - 6.2.3.1 Multiply and Divide with Destination Mode 0
    - 6.2.3.2 E CLASS and Negate Instructions
    - 6.2.3.3 RESET Instruction
    - 6.2.3.4 HALT Instruction
    - 6.2.3.5 WAIT Instruction
    - 6.2.3.6 Processor Status Change Instructions
  - 6.2.4 Destination Mode 0 Sequences
    - 6.2.4.1 Not Register 7
    - 6.2.4.2 Register 7
    - 6.2.4.3 Floating-Point Instruction
  - 6.2.5 Destination Modes 1 Through 3
    - 6.2.5.1 Sequence Entry
    - 6.2.5.2 Destination Modes 1 and 2
    - 6.2.5.3 Destination Mode 3
  - 6.2.6 Destination Modes 4 Through 7
    - 6.2.6.1 Fork C Entries for Modes 4 and 5
    - 6.2.6.2 Fork A Entry for Modes 4 and 5
    - 6.2.6.3 Destination Modes 6 and 7 Entry
    - 6.2.6.4 Ending Sequence
  - 6.2.7 ASH, ASHC, and Floating-Point Instructions
    - 6.2.7.1 ASH Instruction
    - 6.2.7.2 ASHC Instruction
    - 6.2.7.3 Condition Code Loading
    - 6.2.7.4 ASHC Processing
    - 6.2.7.5 Floating-Point Instructions
  - 6.2.8 Multiply Instructions
    - 6.2.8.1 Multiplication Setup
    - 6.2.8.2 Multiplication Process
    - 6.2.8.3 Multiplication Correction
  - 6.2.9 Divide Instruction Sequence
    - 6.2.9.1 Initial Setup
    - 6.2.9.2 Negative Dividend Processing
    - 6.2.9.3 Overflow Test and First Cycle
    - 6.2.9.4 Division Process
    - 6.2.9.5 Remainder Storage and Sign Check
    - 6.2.9.6 Remainder Correction
    - 6.2.9.7 Quotient Sign Change
  - 6.2.10 Memory Reference Execution Sequences
    - 6.2.10.1 Standard Execution
    - 6.2.10.2 Negate Instructions
    - 6.2.10.3 Shifter Instructions
    - 6.2.10.4 Test Instructions
    - 6.2.10.5 Jump Instruction
    - 6.2.10.6 Jump to Subroutine Instruction
    - 6.2.10.7 Move From Previous Space Instruction
  - 6.2.11 Break Conditions Sequences
    - 6.2.11.1 Abort Sequence
    - 6.2.11.2 Break Sequence
    - 6.2.11.3 Power-Up Sequence
    - 6.2.11.4 Internal Traps
    - 6.2.11.5 Stack Errors
    - 6.2.11.6 Internal Vector Generation
    - 6.2.11.7 Interrupts
    - 6.2.11.8 Floating-Point Instructions
    - 6.2.11.9 Trap Instructions
  - 6.2.12 The Service Sequence
    - 6.2.12.1 PC Fetch
    - 6.2.12.2 PS Fetch
    - 6.2.12.3 Stacking Setup
    - 6.2.12.4 Stacking the Old Values
  - 6.2.13 Console Operation Sequences
    - 6.2.13.1 Processor Rest State
    - 6.2.13.2 Load Address Function
    - 6.2.13.3 Register Examine and Deposit
    - 6.2.13.4 Memory Examine and Deposit
    - 6.2.13.5 Start Operation
    - 6.2.13.6 Continue Functions
- 6.3 Following an Instruction Through the Flowcharts
- 6.4 An Instruction Example
Chapter 7 Logic Description
- 7.1 DAP Module M8100
  - 7.1.1 Bus Register
  - 7.1.2 A, B, and Bus Address Multiplexers
  - 7.1.3 Constant Multiplexer 1 (K1MX)
  - 7.1.4 Arithmetic Logic Unit, Shifter, and Program Counter
    - 7.1.4.1 Arithmetic Logic Unit (ALU)
    - 7.1.4.2 Shifters and Program Counter
    - 7.1.4.3 Shifter Logic
    - 7.1.4.4 Program Counter Clocks
    - 7.1.4.5 Control Signals
- 7.2 GRA Module M8101
  - 7.2.1 Arithmetic Logic Unit Control
    - 7.2.1.1 Non-Instruction-Dependent Control
    - 7.2.1.2 Instruction-Dependent Control
  - 7.2.2 Shifter Zero Detection
    - 7.2.2.1 Left Save
    - 7.2.2.2 Odd Byte Destination
  - 7.2.3 General Register Address Logic
    - 7.2.3.1 Source and Destination Address Multiplexers
    - 7.2.3.2 General Register Set Selection
    - 7.2.3.3 General Register Control Signals
  - 7.2.4 General Registers, Source and Destination Multiplexers, and Registers
    - 7.2.4.1 General Registers
    - 7.2.4.2 Source and Destination Multiplexers
    - 7.2.4.3 Source Register (SR)
    - 7.2.4.4 Destination Register (DR)
    - 7.2.4.5 Control Logic
    - 7.2.4.6 Special Signals
    - 7.2.4.7 SR15 and DR15
  - 7.2.5 Shift Counter
- 7.3 IRC Module M8102
  - 7.3.1 Instruction Register (IR)
  - 7.3.2 Fork B Logic
    - 7.3.2.1 Fork B Instructions
    - 7.3.2.2 Fork B Multiplexer
  - 7.3.3 Fork C Logic
    - 7.3.3.1 Fork C Instruction
    - 7.3.3.2 Fork C Multiplexer
  - 7.3.4 CCL Decoding
  - 7.3.5 C Bit Data
  - 7.3.6 N Bit Data
  - 7.3.7 Z Bit Data
    - 7.3.7.1 ZDATA1 Sources
    - 7.3.7.2 ZDATA2 Sources
  - 7.3.8 V Bit Data
    - 7.3.8.1 VEN1
    - 7.3.8.2 VEN2
  - 7.3.9 Condition Code Storage
    - 7.3.9.1 Clocked Inputs
    - 7.3.9.2 BR Inputs
    - 7.3.9.3 IR Inputs
    - 7.3.9.4 Condition Code Subsidiary ROMs
    - 7.3.9.5 ROM Address Multiplexer
    - 7.3.9.6 Subsidiary ROMs
- 7.4 PDR Module M8104
  - 7.4.1 Bus Register Multiplexer
  - 7.4.2 Bus Register A and Light Register
  - 7.4.3 Program Break Register
  - 7.4.4 Stack Limit Register
  - 7.4.5 Program Interrupt Register
  - 7.4.6 Processor Status Register
    - 7.4.6.1 Condition Codes
    - 7.4.6.2 T Bit
    - 7.4.6.3 Priority Bits
    - 7.4.6.4 General Register Set Bit
    - 7.4.6.5 Previous Mode Bits
    - 7.4.6.6 Current Mode Bits
    - 7.4.6.7 Read PS
  - 7.4.7 Unibus A Data Multiplexer
  - 7.4.8 Display Multiplexer
  - 7.4.9 Console Interconnections
- 7.5 RAC Module M8103
  - 7.5.1 ROM Address Register (RAR)
  - 7.5.2 Microprogram ROM and Buffer Register
  - 7.5.3 Fork A Instruction Decoding
    - 7.5.3.1 Decode Logic
    - 7.5.3.2 Address Bit Generation
    - 7.5.3.3 RACE A0 RAB <02:00>
    - 7.5.3.4 RACE A0 RAB03
    - 7.5.3.5 RACE A0 RAB04
    - 7.5.3.6 RACE A0 RAB05
  - 7.5.4 Fork A Circuits
    - 7.5.4.1 HALT Through Op Code 7
    - 7.5.4.2 X Class
    - 7.5.4.3 U Class
    - 7.5.4.4 RTS Through CCOP
    - 7.5.4.5 RACF A2 RAB03
    - 7.5.4.6 TRUE 1:2
  - 7.5.5 Fork A Logic
    - 7.5.5.1 Branch Instruction Address Generation
    - 7.5.5.2 Disable BUST
  - 7.5.6 A Fork Instruction Register
  - 7.5.7 Microprogram Branch Logic
  - 7.5.8 Microprogram Address Assembly
- 7.6 TMC Module M8105
  - 7.6.1 Request Storage
    - 7.6.1.1 BRQ Clock
    - 7.6.1.2 Priority Clear
    - 7.6.1.3 Power Fail Clear
    - 7.6.1.4 Internal Bus Initialization
  - 7.6.2 Priority Arbitration
  - 7.6.3 Control Logic
    - 7.6.3.1 BRQ TRUE
    - 7.6.3.2 Enable Vector
    - 7.6.3.3 Branch Enable 13 (BE13)
  - 7.6.4 Odd Address Vector
  - 7.6.5 Fatal Stack Violation
    - 7.6.5.1 Red Zone or Stack Limit Violation
    - 7.6.5.2 Internal Address Violation
  - 7.6.6 Warning Stack Violation
  - 7.6.7 Abort Detection
    - 7.6.7.1 KERNEL R6
    - 7.6.7.2 Address Error Flag (AERF)
    - 7.6.7.3 Stack Error Flag (SERF)
    - 7.6.7.4 Block Strobe
  - 7.6.8 Internal Address Decoder
  - 7.6.9 DMX Select
  - 7.6.10 Bus Condition Multiplexer
  - 7.6.11 Miscellaneous Control and Bus Delay Signals
  - 7.6.12 Internal Bus Signals
  - 7.6.13 Bus Register Multiplexer Control
- 7.7 UBC Module M8106
  - 7.7.1 Bus Control Introduction
    - 7.7.1.1 BUST (Bus Start) Cycle
    - 7.7.1.2 PAUSE Cycle
    - 7.7.1.3 Unibus Control
  - 7.7.2 DATI and DATIP Unibus Transactions
    - 7.7.2.1 CPBSY
    - 7.7.2.2 Address Deskew
    - 7.7.2.3 MSYN
    - 7.7.2.4 Bus Pause and DATI
    - 7.7.2.5 Bus Long Pause and DATI or DATIP
    - 7.7.2.6 BUS LOAD
    - 7.7.2.7 DLP DESKEW
    - 7.7.2.8 BUSA BBSY L
    - 7.7.2.9 TIMEOUT
  - 7.7.3 DATO and DATOB Unibus Transactions
  - 7.7.4 Fastbus Transactions
  - 7.7.5 Fastbus DATI and DATIP
  - 7.7.6 Fastbus DATO and DATOB
  - 7.7.7 Parity Error Logic
  - 7.7.8 NPR and NPG
  - 7.7.9 Priority Bus Requests
    - 7.7.9.1 NO SACK
    - 7.7.9.2 INTR RESTART
  - 7.7.10 Interrupt Flag
  - 7.7.11 Internal SSYN
  - 7.7.12 Data Transfer Control Decoding
    - 7.7.12.1 HY BYTE/LO BYTE
    - 7.7.12.2 CC DATA
  - 7.7.13 Power Control
    - 7.7.13.1 Power Down
    - 7.7.13.2 Power Up
  - 7.7.14 Initialization
    - 7.7.14.1 Power-Down/Power-Up
    - 7.7.14.2 CNSL RESET
    - 7.7.14.3 START
    - 7.7.14.4 RESET ABORT
    - 7.7.14.5 RESET in Progress
  - 7.7.15 Console Switch Inputs
    - 7.7.15.1 DEC Data Center Inputs
    - 7.7.15.2 Console Control Register
  - 7.7.16 Console Control Decoder
    - 7.7.16.1 EXAM and STEP EXAM
    - 7.7.16.2 DEPOSIT and STEP DEPOSIT
- 7.8 TIG Module M8109
  - 7.8.1 Timing Sources
    - 7.8.1.1 Crystal Clock
    - 7.8.1.2 R/C Clock
    - 7.8.1.3 MAINT STPR Switch
  - 7.8.2 Source Synchronizer
    - 7.8.2.1 Crystal Clock Selection
    - 7.8.2.2 RC Clock Selection
    - 7.8.2.3 MAINT STPR Selection
    - 7.8.2.4 Synchronization
  - 7.8.3 Phase Splitter/Buffer
    - 7.8.3.1 Level Converter
    - 7.8.3.2 Phase Splitter
    - 7.8.3.3 Buffers
  - 7.8.4 Timing Generator
  - 7.8.5 STOP T1
    - 7.8.5.1 Not In T4 or T5
    - 7.8.5.2 Semiconductor Memory Delay
    - 7.8.5.3 Conventional Memory Delay
    - 7.8.5.4 Operating System Test
    - 7.8.5.5 Single Cycle Mode
  - 7.8.6 STOP T3
    - 7.8.6.1 Not In T2
    - 7.8.6.2 Single Cycle
    - 7.8.6.3 ROM + UPB
    - 7.6.6.4 Bus Pause or Long Pause Delay
    - 7.8.6.5 Interrupt Pause Delay
    - 7.8.6.6 Operating System Tester
    - 7.8.6.7 KT11-C Delay
  - 7.8.7 Timing Pulse Generators
    - 7.8.7.1 Positive Timing Pulse Generators
    - 7.8.7.2 Negative Timing Pulse Generators
  - 7.8.8 Timing State Generators
- 7.9 Console Logic
  - 7.9.1 Switch Register and Data Display
    - 7.9.1.1 Switch Register Inputs
    - 7.9.1.2 DATA Display
  - 7.9.2 Address Display and Control
    - 7.9.2.1 Address Bits <05:00>
    - 7.9.2.2 Address Bits <15:06>
    - 7.9.2.3 Address Bits <17:16>
  - 7.9.3 Console Mode Control
- 7.10 SJB Module M8116
Chapter 8 Maintenance

Company:	Digital Equipment Corporation
Part:	DEC-11-HKBB-D
Date:	1972-07
Keywords:	PDP-11
Superseded by:	DEC-11-HKBAA-B-D, KB11-A Central Processor Unit Maintenance Manual
Cited by:	DEC-11-HKTCA-C-D, KT11-C Memory Management Unit Maintenance Manual

Address:	http://bitsavers.org/pdf/dec/pdp11/1145/KB11-A_Maint.pdf
Site:	Al Kossow's Bitsavers
Format:	PDF
Size:	14023904 bytes (13.4 MiB)

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KB11-A Central Processor Unit Maintenance Manual

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