KA11 Processor Manual

Chapter 1 Block Diagrams
- 1.1 Basic Block Diagram
  - 1.1.1 Data Sections
  - 1.1.2 Control Section
  - 1.1.3 The Unibus
  - 1.1.4 Summary Description
- 1.2 Bit-Slice Block Diagram
  - 1.2.1 Control Signals
  - 1.2.2 Structure of the Data Flow
    - 1.2.2.1 Latches
    - 1.2.2.2 Adders
    - 1.2.2.3 Output Gating
  - 1.2.3 Registers and Bus Interface
    - 1.2.3.1 Registers
    - 1.2.3.2 Bus Interface
- 1.3 Module Block Diagram
  - 1.3.1 Module Distribution
  - 1.3.2 Processor Structure
  - 1.3.3 Control Section
    - 1.3.3.1 Machine State Storage
    - 1.3.3.2 Machine State Selection
    - 1.3.3.3 Control Signal Generation
Chapter 2 The Instruction Set
- 2.1 Purpose
- 2.2 Scope
- 2.3 ISP Notation
- 2.4 PDP-11 Data Structure
- 2.5 Address Modes
- 2.6 Instruction Execution Process
Chapter 3 Machine State Flow Charts
- 3.1 Purpose of the Flow Charts
- 3.2 Information in the Flow Charts
  - 3.2.1 Current Machine State
  - 3.2.2 Input Information
  - 3.2.3 Next Machine State
  - 3.2.4 Output Signals
- 3.3 A Note on Processor Description
- 3.4 Flow Chart Organization
- 3.5 Processor Timing
- 3.6 Major State Flow
  - 3.6.1 Fetch
  - 3.6.2 Source and Destination
  - 3.6.3 Execute
  - 3.6.4 Service
- 3.7 Unibus Operations
  - 3.7.1 Processor Control of Data Transfers
  - 3.7.2 BSR1
  - 3.7.3 BSR3
  - 3.7.4 BSR7
  - 3.7.5 BSR15 and 14
  - 3.7.6 BSR0 for Output Transfers
  - 3.7.7 BSR12
  - 3.7.8 BSR8
- 3.8 Fetch Major State
- 3.9 Operand Access Major States
  - 3.9.1 Address Modes
    - 3.9.1.1 Address Mode 1
    - 3.9.1.2 Address Mode 2
    - 3.9.1.3 Address Mode 3
    - 3.9.1.4 Address Mode 4
    - 3.9.1.5 Address Mode 5
    - 3.9.1.6 Address Mode 6
    - 3.9.1.7 Address Mode 7
  - 3.9.2 Disposition of the Operand
  - 3.9.3 Entries to and Exits from Source and Destination
- 3.10 Execute Major State
  - 3.10.1 Data Manipulation Instructions
    - 3.10.1.1 Entries into Execute
    - 3.10.1.2 The Extra ISR States
    - 3.10.1.3 Disposition of the Result
  - 3.10.2 JSR Instructions
  - 3.10.3 Branch Instructions
  - 3.10.4 RTS Instruction
  - 3.10.5 RTI Instruction
- 3.11 Service Major State
  - 3.11.1 Condition Code Clocking in ISR2
  - 3.11.2 Priorities for Service in ISR0
  - 3.11.3 Wait Service
  - 3.11.4 Request Service
  - 3.11.5 Interrupt Recognition
  - 3.11.6 Trap and Interrupt Service
    - 3.11.6.1 ISR1
    - 3.11.6.2 ISR3
    - 3.11.6.3 ISR7
    - 3.11.6.4 ISR15 and ISR14
    - 3.11.6.5 ISR12 and ISR8
    - 3.11.6.6 Exits from the Service Sequence
- 3.12 Operations Done When the Halt Flag is Set
Chapter 4 KA11 Processor Logic Description
- 4.1 Introduction
- 4.2 Print Organization
- 4.3 Logic Usage
- 4.4 Logic Discussions
- 4.5 Timing & States
- 4.6 State CNTL
- 4.7 Priority, M824
  - 4.7.1 Priority
  - 4.7.2 Power Fail
  - 4.7.3 Bus Receivers and Drivers
- 4.8 Register CNTL, M821
- 4.9 Register, M225
- 4.10 Data Path CNTL
  - 4.10.1 Register Data Transfer
  - 4.10.2 Unibus Data Transfer
- 4.11 Data Paths, M224
  - 4.11.1 General
  - 4.11.2 Input Gating and Latches
  - 4.11.3 Adder
  - 4.11.4 Rotate/Shift Gating
- 4.12 Data Paths 1
- 4.13 Data Paths, M224
  - 4.13.1 General
  - 4.13.2 Input Gating and Latches
  - 4.13.3 Adder
  - 4.13.4 Rotate/Shift Gating
- 4.14 Data Paths 2
- 4.15 Bus Interface & IR
- 4.16 IR Decode
- 4.17 Codes Data, M823
  - 4.17.1 General
  - 4.17.2 Output Signals
- 4.18 Flag CNTL, M822
- 4.19 Bus & Console CNTL
- 4.20 PWR FAIL & CNTL, M825
  - 4.20.1 Power Fail
  - 4.20.2 General Control Gating
Chapter 5 Maintenance
- 5.1 Scope
- 5.2 Test Equipment and Tools
- 5.3 Installation of ECOs
- 5.4 Module Identification and Layout
- 5.5 Module Component Identification
- 5.6 Unibus Connections
- 5.7 Multiple Box Systems
- 5.8 Power Control
- 5.9 Processor Clock Adjustment
- 5.10 Removal/Installation
- 5.11 Maintenance Tips
  - 5.11.1 Diagnostic Programs
  - 5.11.2 KM11 Maintenance Set
  - 5.11.3 Observation of Service Major State Operation

Company:	Digital Equipment Corporation
Part:	DEC-11-HR2A-D
Date:	1970-09
Keywords:	PDP-11
Cited by:	DEC-11-HDBA-D, DB11-A Bus Repeater Manual

Address:	http://bitsavers.org/pdf/dec/pdp11/1120/KA11_ProcessorMan_Sep1970.pdf
Site:	Al Kossow's Bitsavers
Format:	PDF
Size:	13924085 bytes (13.3 MiB)

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KA11 Processor Manual

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