KB11-A,D Central Processor Unit Maintenance Manual

Chapter 1 Introduction
- 1.1 General
- 1.2 KB11-D vs. KB11-A
- 1.3 Related Documents
Chapter 2 General Description
- 2.1 Basic System Description
  - 2.1.1 A Faster Basic System
  - 2.1.2 A Virtual Machine System
- 2.2 Functional Description
  - 2.2.1 Data Manipulation
  - 2.2.2 Transferring Data
  - 2.2.3 Handling Instructions
  - 2.2.4 Handling Asynchronous Conditions
Chapter 3 Concepts
- 3.1 Microprogramming
  - 3.1.1 Digital Computer Description
  - 3.1.2 The Data Section
    - 3.1.2.1 The Data Storage Section
    - 3.1.2.2 The Data Manipulation Section
    - 3.1.2.3 The Data Routing Section
    - 3.1.2.4 The Data Section in the KB11-A, D
  - 3.1.3 The Control Section
    - 3.1.3.1 The Sequence Control Section
    - 3.1.3.2 The Function Generator
    - 3.1.3.3 The Sensing Logic
    - 3.1.3.4 The Control Section in the KB11-A, D
  - 3.1.4 Microprogramming in the Control Section Implementation
    - 3.1.4.1 Conventional Implementation
    - 3.1.4.2 Microprogrammed Implementation
- 3.2 Parallel Operation (Pipelining)
- 3.3 Virtual Machines
  - 3.3.1 Mapping
  - 3.3.2 Resource Management
    - 3.3.2.1 Process Management
    - 3.3.2.2 Memory Management
    - 3.3.2.3 Memory Use Statistics
  - 3.3.3 Communication
    - 3.3.3.1 Context Switching
    - 3.3.3.2 Inter-Program Data Transfers
    - 3.3.3.3 Returning to the Previous Context
  - 3.3.4 Protection
    - 3.3.4.1 Separate Address Spaces
    - 3.3.4.2 Access Modes
    - 3.3.4.3 Privileged Instructions
- 3.4 Re-Entrant and Recursive Programming
  - 3.4.1 Recursive Functions
  - 3.4.2 Use of a Stack in Recursive Routines
  - 3.4.3 Re-Entrant Functions
  - 3.4.4 Indexed Addressing of Parameters
  - 3.4.5 Separate Stack and Index Pointers
  - 3.4.6 Subroutine Call Compatibility
  - 3.4.7 The MARK Instruction
- 3.5 Processor Status Operations
  - 3.5.1 Current Processor Mode
  - 3.5.2 Previous Processor Mode
  - 3.5.3 Register Set Selection
  - 3.5.4 Processor Priority
    - 3.5.4.1 Device Priorities
    - 3.5.4.2 Program Priorities
    - 3.5.4.3 Programmed Interrupt Requests
  - 3.5.5 The Trace Bit
  - 3.5.6 The Condition Codes
- 3.6 Stack Limit Protection
- 3.7 The Multiply and Divide Instructions
  - 3.7.1 Number Representation
  - 3.7.2 The Multiply Algorithm
  - 3.7.3 Sign Correction During Multiplication
  - 3.7.4 The Divide Instruction
Chapter 4 Block Diagram Description
- 4.1 Data Paths Block Diagram
- 4.2 General Storage Registers
  - 4.2.1 Program Counter (PC)
  - 4.2.2 Stack Pointers (SP)
  - 4.2.3 General Register Sets
- 4.3 Temporary Storage Registers
  - 4.3.1 Source Register (SR)
  - 4.3.2 Destination Register (DR)
  - 4.3.3 Bus Register (BR and BRA)
- 4.4 Special Purpose Registers
  - 4.4.1 Instruction Register (IR)
  - 4.4.2 Shift Counter (SC)
  - 4.4.3 Processor Status Register (PS)
  - 4.4.4 Programmed Interrupt Request Register (PIRQ)
  - 4.4.5 Stack Limit Register (SL)
  - 4.4.6 Microprogram Break Register (PB)
  - 4.4.7 Console Switches (SW) and Light Register (LR)
- 4.5 Data Manipulation
  - 4.5.1 Arithmetic and Logic Unit (ALU)
  - 4.5.2 Shifter (SHFR)
  - 4.5.3 Constant Multiplexers (K0MX, K1MX)
  - 4.5.4 Destination Register (DR)
  - 4.5.5 Shift Counter (SC)
- 4.6 Data Routing Elements
  - 4.6.1 ALU Interface Multiplexers
  - 4.6.2 Temporary Storage Register Input Multiplexers
  - 4.6.3 External Interface Multiplexers
- 4.7 Control Section
  - 4.7.1 ROM Microprogram Control
  - 4.7.2 External Interface Control
    - 4.7.2.1 Unibus and Console Control (UBC) Module
    - 4.7.2.2 Traps and Miscellaneous Control (TBC) Module
    - 4.7.2.3 The Timing Generator (TIG) Module
- 4.8 Special Control Logic
  - 4.8.1 Arithmetic and Logic Unit (ALU) Control
  - 4.8.2 Condition Code Control
  - 4.8.3 General Register Control
Chapter 5 Address Modes and Instruction Sets
- 5.1 Address Modes
- 5.2 KB11-A, D Instructions
- 5.3 KB11-A, D Instruction Time
  - 5.3.1 Approaches -- Typical/Minimum/Maximum/Measured
  - 5.3.2 Steps to Calculate Instruction Times
    - 5.3.2.1 Step 1: Subcycle Times
    - 5.3.2.2 Step 2: Cycle Times
    - 5.3.2.3 Step 3: Instruction Time
  - 5.3.3 Determining Subcycle Times
    - 5.3.3.1 MSYN Generation Time (TMS)
    - 5.3.3.2 MSYN Generation Time Delayed (TMSD)
    - 5.3.3.3 MM11-L Access Time (TA)
    - 5.3.3.4 MM11-L Cycle Time (TC)
    - 5.3.3.5 Unibus Propagation Delay (TP)
    - 5.3.3.6 SSYN Resync Time (TSS)
  - 5.3.4 Calculating Cycle Times
    - 5.3.4.1 DATI and DATIP
    - 5.3.4.2 DATO
    - 5.3.4.3 DATI or DATIP with Immediately Previous DATO
    - 5.3.4.4 DATI or DATIP with Immediately Previous DATI
    - 5.3.4.5 DATO with Immediately Previous DATI
    - 5.3.4.6 DATO with Immediately Previous DATO
    - 5.3.4.7 DATO (with TMSD)
  - 5.3.5 Example of Calculating an Instruction Time
    - 5.3.5.1 Step 1
    - 5.3.5.2 Step 2
    - 5.3.5.3 Step 3
  - 5.3.6 Comments on the Instruction Times Table (PDP-11/04, 05, 10, 35, 40, 45 Processor Handbook)
  - 5.3.7 KB11-A, D Cycle Delays and Speed Variation
    - 5.3.7.1 Basic Memory Cycle
    - 5.3.7.2 Effect of Previous Cycle Memory Busy
    - 5.3.7.3 Fast Processor
    - 5.3.7.4 Slow Processor
Chapter 6 Operation
- 6.1 Console Controls and Indicators
- 6.2 Power On
  - 6.2.1 ENABL Function
  - 6.2.2 HALT Function
- 6.3 Console Operations
  - 6.3.1 HALT Switch Functions
    - 6.3.1.1 HALT/CONT with S INST
    - 6.3.1.2 HALT/CONT with S BUS CYCLE
  - 6.3.2 EXAM Switch Functions
  - 6.3.3 DEP Switch Functions
  - 6.3.4 REG EXAM and REG DEP Functions
- 6.4 Address Display Select
  - 6.4.1 PROG PHY Function
  - 6.4.2 CONS PHY Function
  - 6.4.3 USER, SUPER, or KERNEL Functions
- 6.5 How To Load And Run Programs
  - 6.5.1 Loading the PDP-11 Bootstrap Loader
  - 6.5.2 Loading the PDP-11 Absolute Binary Loader
  - 6.5.3 Loading the Maintenance Loader
Chapter 7 KB11-A, D Flows
- 7.1 Flow Diagrams
  - 7.1.1 ROM Timing
  - 7.1.2 Glossary
- 7.2 A and C Forks: Operand Fetch
- 7.3 Flowchart Description
  - 7.3.1 Flows 1
  - 7.3.2 Flows 2
  - 7.3.3 Flows 3
  - 7.3.4 Flows 4
  - 7.3.5 Flows 5
  - 7.3.6 Flows 6
  - 7.3.7 Flows 7
  - 7.3.8 Flows 8
  - 7.3.9 Flows 9 and 10
  - 7.3.10 Flows 11
  - 7.3.11 Flows 12 and 13
  - 7.3.12 Flows 14
- 7.4 Following An Instruction Through the Flowcharts
  - 7.4.1 Figures and Tables
Chapter 8 Logic Description
- 8.1 DAP Module M8100
  - 8.1.1 Bus Register
  - 8.1.2 A, B, and Bus Address Multiplexers
  - 8.1.3 Constant Multiplexer 1 (K1MX)
  - 8.1.4 Arithmetic Logic Unit, Shifter, and Program Counter
    - 8.1.4.1 Arithmetic Logic Unit (ALU)
    - 8.1.4.2 Shifters and Program Counter
    - 8.1.4.3 Shifter Logic
    - 8.1.4.4 Program Counter Clocks
    - 8.1.4.5 Control Signals
- 8.2 GRA Module M8101
  - 8.2.1 Arithmetic and Logic Unit Control
    - 8.2.1.1 Non-Instruction-Dependent Control
    - 8.2.1.2 Instruction-Dependent Control
  - 8.2.2 Shifter Zero Detection
    - 8.2.2.1 Left Save
    - 8.2.2.2 Odd Byte Destination
  - 8.2.3 General Register Address Logic
    - 8.2.3.1 Source and Destination Address Multiplexers
    - 8.2.3.2 General Register Set Selection
    - 8.2.3.3 General Register Control Signals
  - 8.2.4 General Registers, Source and Destination Multiplexers, and Registers
    - 8.2.4.1 General Registers
    - 8.2.4.2 Source and Destination Multiplexers
    - 8.2.4.3 Source Register (SR)
    - 8.2.4.4 Destination Register (DR)
    - 8.2.4.5 Control Logic
    - 8.2.4.6 Special Signals
    - 8.2.4.7 SR15 and DR15
  - 8.2.5 Shift Counter
- 8.3 IRC Module (M8102 in the KB11-A, M8132 in the KB11-D)
  - 8.3.1 Instruction Register (IR)
  - 8.3.2 B Fork Logic
  - 8.3.3 C Fork Logic
  - 8.3.4 CCL Decoding
  - 8.3.5 C Bit Data
  - 8.3.6 N Bit Data
  - 8.3.7 Z Bit Data
    - 8.3.7.1 ZDATA1 Sources
    - 8.3.7.2 ZDATA2 Sources
  - 8.3.8 V Bit Data
    - 8.3.8.1 VEN1
    - 8.3.8.2 VEN2
  - 8.3.9 Condition Code Storage
    - 8.3.9.1 Clocked Inputs
    - 8.3.9.2 BR Inputs
    - 8.3.9.3 IR Inputs
    - 8.3.9.4 Subsidiary ROMs Address Generation
    - 8.3.9.5 ROM Address Multiplexer
    - 8.3.9.6 Subsidiary ROMs
- 8.4 PDR Module M8104
  - 8.4.1 Bus Register Multiplexer
  - 8.4.2 Bus Register A and Light Register
  - 8.4.3 Program Break Register
  - 8.4.4 Stack Limit Register
  - 8.4.5 Program Interrupt Register
  - 8.4.6 Processor Status Register
    - 8.4.6.1 Condition Codes
    - 8.4.6.2 T Bit
    - 8.4.6.3 Priority Bits
    - 8.4.6.4 General Register Set Bit
    - 8.4.6.5 Previous Mode Bits
    - 8.4.6.6 Current Mode Bits
    - 8.4.6.7 Read PS
  - 8.4.7 Unibus A Data Multiplexer
  - 8.4.8 Display Multiplexer
  - 8.4.9 Console Interconnections
- 8.5 RAC Module (M8103 in the KB11-A, M8123 in the KB11-D)
  - 8.5.1 ROM Address Register (RAR)
  - 8.5.2 Microprogram ROM and Buffer Register
  - 8.5.3 Fork A Instruction Decoding
    - 8.5.3.1 Decode Logic
    - 8.5.3.2 Address Bit Generation
    - 8.5.3.3 RACE A0 RAB <02:00>
    - 8.5.3.4 RACE A0 RAB03
    - 8.5.3.5 RACE A0 RAB04
    - 8.5.3.6 RACE A0 RAB05
  - 8.5.4 Fork A Circuits
    - 8.5.4.1 HALT Through Op Code 7
    - 8.5.4.2 X Class
    - 8.5.4.3 U Class
    - 8.5.4.4 RTS Through CCOP
    - 8.5.4.5 RACF A2 RAB03
    - 8.5.4.6 TRUE 1:2
  - 8.5.5 Fork A Logic
    - 8.5.5.1 Branch Instruction Address Generation
    - 8.5.5.2 Disable BUST
  - 8.5.6 A Fork Instruction Register
  - 8.5.7 Microprogram Branch Logic
  - 8.5.8 Microprogram Address Assembly
- 8.6 TMC Module M8105
  - 8.6.1 Request Storage
    - 8.6.1.1 BRQ Clock
    - 8.6.1.2 Priority Clear
    - 8.6.1.3 Power Fail Clear
    - 8.6.1.4 Internal Bus Initialization
  - 8.6.2 Priority Arbitration
  - 8.6.3 Control Logic
    - 8.6.3.1 BRQ TRUE
    - 8.6.3.2 Enable Vector
    - 8.6.3.3 Branch Enable 13 (BE13)
  - 8.6.4 Odd Address Error
  - 8.6.5 Fatal Stack Violation
    - 8.6.5.1 Red Zone or Stack Limit Violation
    - 8.6.5.2 Internal Address Violation
  - 8.6.6 Warning Stack Violation
  - 8.6.7 Abort Detection
    - 8.6.7.1 KERNEL R6
    - 8.6.7.2 Address Error Flag (AERF)
    - 8.6.7.3 Stack Error Flag (SERF)
    - 8.6.7.4 Block Strobe
  - 8.6.8 Internal Address Decoder
  - 8.6.9 DMX Select
    - 8.6.10 Bus Condition Multiplexer
    - 8.6.11 Miscellaneous Control and Bus Delay Signals
    - 8.6.12 Internal Bus Signals
    - 8.6.13 Bus Register Multiplexer Control
- 8.7 UBC Module (M8106 in the KB11-A, M8119 in the KB11-D)
  - 8.7.1 Bus Control Introduction
    - 8.7.1.1 BUST (Bus Start) Cycle
    - 8.7.1.2 PAUSE Cycle
    - 8.7.1.3 Unibus Control
  - 8.7.2 DATI and DATIP Unibus Transactions
    - 8.7.2.1 CPBSY
    - 8.7.2.2 Address Deskew
    - 8.7.2.3 MSYN
    - 8.7.2.4 Bus Pause and DATI or DATIP, Early KB11-A Units
    - 8.7.2.5 Bus Pause and DATI or DATIP in the KB11-D and Later KB11-A Units
    - 8.7.2.6 TIMEOUT
  - 8.7.3 DATO and DATOB Unibus Transactions
    - 8.7.3.1 Early KB11-A machines
    - 8.7.3.2 DATO and DATOB in the KB11-D and the KB11-A with ECO KB11-A No. 13
  - 8.7.4 Fastbus Transactions
  - 8.7.5 Fastbus DATI and DATIP
  - 8.7.6 Fastbus DATO and DATOB
  - 8.7.7 Parity Error Logic
  - 8.7.8 NPR and NPG
  - 8.7.9 Priority Bus Request
    - 8.7.9.1 NO SACK
    - 8.7.9.2 INTR RESTART
  - 8.7.10 Interrupt Flag
  - 8.7.11 Internal SSYN
  - 8.7.12 Data Transfer Control Decoding
    - 8.7.12.1 HI BYTE/LO BYTE
    - 8.7.12.2 CC DATA
  - 8.7.13 Power Control
    - 8.7.13.1 Power Down
    - 8.7.13.2 Power Up
  - 8.7.14 Initialization
    - 8.7.14.1 Power-Down/Power-Up
    - 8.7.14.2 Console Start and Reset
  - 8.7.15 Console Switch Inputs
    - 8.7.15.1 DEC Data Center Inputs
    - 8.7.15.2 Console Control Register
  - 8.7.16 Console Control Decoder
    - 8.7.16.1 EXAM and STEP EXAM
    - 8.7.16.2 DEPOSIT and STEP DEPOSIT
    - 8.7.16.3 REGISTER EXAM, DEPOSIT, STEP EXAM, STEP DEPOSIT
- 8.8 TIG Module M8109
  - 8.8.1 Timing Sources
    - 8.8.1.1 Crystal Clock
    - 8.8.1.2 R/C Clock
    - 8.8.1.3 MAINT STPR Switch
  - 8.8.2 Source Synchronizer
    - 8.8.2.1 Crystal Clock Selection
    - 8.8.2.2 RC Clock Selection
    - 8.8.2.3 MAINT STPR Selection
    - 8.8.2.4 Synchronization
  - 8.8.3 Phase Splitter/Buffer
    - 8.8.3.1 Level Converter
    - 8.8.3.2 Phase Splitter
    - 8.8.3.3 Buffers
  - 8.8.4 Timing Generator
  - 8.8.5 STOP T1
    - 8.8.5.1 Not In T4 or T5
    - 8.8.5.2 Semiconductor Memory Delay
    - 8.8.5.3 Conventional Memory Delay
    - 8.8.5.4 Operating System Test
    - 8.8.5.5 Single Cycle Mode
  - 8.8.6 STOP T3
    - 8.8.6.1 Not In T2
    - 8.8.6.2 Single Cycle
    - 8.8.6.3 ROM + UPB
    - 8.8.6.4 Bus Pause or Long Pause Delay
    - 8.8.6.5 Interrupt Pause Delay
    - 8.8.6.6 Operating System Tester
    - 8.8.6.7 KT11-C, CD Delay
  - 8.8.7 Timing Pulse Generators
    - 8.8.7.1 Postive Timing Pulse Generators
    - 8.8.7.2 Negative Timing Pulse Generators
  - 8.8.8 Timing State Generators
- 8.9 Console Logic
  - 8.9.1 Switch Register and Data Display
    - 8.9.1.1 Switch Register Inputs
    - 8.9.1.2 DATA Display
  - 8.9.2 Address Display and Control
    - 8.9.2.1 Address Bits <05:00>
    - 8.9.2.2 Address Bits <15:06>
    - 8.9.2.3 Address Bits <17:16>
  - 8.9.3 Console Mode Control
- 8.10 SJB Module M8116
Chapter 9 Maintenance
- 9.1 General
- 9.2 KB11-A, D CPU Diagnostics
Appendix A IC Descriptions

Company:	Digital Equipment Corporation
Part:	EK-KB11A-MM-004
Date:	1976-08
Keywords:	PDP-11/45 KB11-D
Cited by:	EK-KT11C-MM-005, KT11-C, CD Memory Management Unit Maintenance Manual
Mentions:	EK-11045-MM-007, PDP-11/45, 11/50, and 11/55 System Maintenance Manual EK-FP11C-MM-001, FP11-C Floating-Point Processor Maintenance Manual EK-FP11-MM-003, FP11-B Floating-Point Processor Maintenance Manual EK-MS11A-MM-005, MS11-A,B,C Memory Systems Maintenance Manual EK-KT11C-MM-005, KT11-C, CD Memory Management Unit Maintenance Manual EB-05138-75, PDP-11 04/05/10/35/40/45 Processor Handbook EB-05117-060, PDP-11 Peripherals Handbook

Address:	http://bitsavers.org/pdf/dec/pdp11/1145/EK-KB11A-MM-004_Aug76.pdf
Site:	Al Kossow's Bitsavers
Format:	PDF
Size:	14567098 bytes (13.9 MiB)

Address:	http://www.vaxhaven.com/images/9/9e/EK-KB11A-MM-004.pdf
Site:	VaxHaven
Format:	PDF
Size:	14567098 bytes (13.9 MiB)

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KB11-A,D Central Processor Unit Maintenance Manual

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