VAX-11 Architecture Reference Manual

Chapter 1 Introduction
- 1.1 Introduction
- 1.2 Terminology and Conventions
  - 1.2.1 Numbering
  - 1.2.2 UNPREDICTABLE and UNDEFINED
  - 1.2.3 Ranges and Extents
  - 1.2.4 MBZ
  - 1.2.5 Reserved
  - 1.2.6 Figure Drawing Conventions
Chapter 2 Basic Architecture
- 2.1 Addressing
- 2.2 Data Types
  - 2.2.1 Byte
  - 2.2.2 Word
  - 2.2.3 Longword
  - 2.2.4 Quadword
  - 2.2.5 Octaword
  - 2.2.6 F_floating
  - 2.2.7 D_floating
  - 2.2.8 G_floating
  - 2.2.9 H_floating
  - 2.2.10 Variable Length Bit Field
  - 2.2.11 Character String
  - 2.2.12 Trailing Numeric String
  - 2.2.13 Leading Separate Numeric String
  - 2.2.14 Packed Decimal String
- 2.3 Processor State
- 2.4 Processor Status Word
  - 2.4.1 C Bit
  - 2.4.2 V Bit
  - 2.4.3 Z Bit
  - 2.4.4 N Bit
  - 2.4.5 T Bit
  - 2.4.6 IV Bit
  - 2.4.7 FU Bit
  - 2.4.8 DV Bit
- 2.5 Permanent Exception Enables
  - 2.5.1 Divide By Zero
  - 2.5.2 Floating Overflow
- 2.6 Instruction Format
- 2.7 Separation of Procedure and Data
- 2.8 I/O Structure
- 2.9 Interrupt Structure
Chapter 3 Instruction Formats and Addressing Modes
- 3.1 Opcode Formats
- 3.2 Operand Specifiers
- 3.3 Notation
- 3.4 General Mode Addressing Formats
  - 3.4.1 Register Mode
  - 3.4.2 Register Deferred Mode
  - 3.4.3 Autoincrement Mode
  - 3.4.4 Autoincrement Deferred Mode
  - 3.4.5 Autodecrement Mode
  - 3.4.6 Displacement Mode
  - 3.4.7 Displacement Deferred Mode
  - 3.4.8 Literal Mode
  - 3.4.9 Index Mode
- 3.5 Summary of General Mode Addressing
  - 3.5.1 General Register Addressing
  - 3.5.2 Program Counter Addressing (reg=15)
- 3.6 Branch Mode Addressing Formats
- 3.7 Operand Specifier Conventions
Chapter 4 Instructions
- 4.1 Instruction Set
  - 4.1.1 Instruction Descriptions
  - 4.1.2 Operand Specifier Notation
  - 4.1.3 Operation Description Notation
- 4.2 Integer Arithmetic and Logical Instructions
- 4.3 Address Instructions
- 4.4 Variable Length Bit Field Instructions
- 4.5 Control Instructions
- 4.6 Procedure Call Instructions
- 4.7 Miscellaneous Instructions
- 4.8 Queue Instructions
  - 4.8.1 Absolute Queues
  - 4.8.2 Self-relative Queues
  - 4.8.3 Instruction Descriptions
- 4.9 Floating Point Instructions
  - 4.9.1 Introduction
  - 4.9.2 Overview of the Instruction Set
  - 4.9.3 Accuracy
  - 4.9.4 Instruction Descriptions
- 4.10 Character String Instructions
- 4.11 Cyclic Redundancy Check Instruction
- 4.12 Decimal String Instructions
  - 4.12.1 Decimal Overflow
  - 4.12.2 Zero Numbers
  - 4.12.3 Reserved Operand Exception
  - 4.12.4 UNPREDICTABLE Results
  - 4.12.5 Packed Decimal Operations
  - 4.12.6 Zero Length Decimal Strings
  - 4.12.7 Instruction Descriptions
- 4.13 EDIT Instruction
- 4.14 Other VAX-11 Instructions
Chapter 5 Memory Management
- 5.1 Introduction
- 5.2 Virtual Address Space
  - 5.2.1 Process Space
  - 5.2.2 System Space
  - 5.2.3 Virtual Address Format
  - 5.2.4 Virtual Address Space Layout
- 5.3 Memory Management Control
  - 5.3.1 Memory Management Disabled
- 5.4 Address Translation
  - 5.4.1 Page Table Entry (PTE)
  - 5.4.2 Page Table Entry (PTE) For I/O Devices
  - 5.4.3 Changes To Page Table Entries
- 5.5 Access Control
  - 5.5.1 Processor Modes
  - 5.5.2 Protection Code
  - 5.5.3 Length Violation
  - 5.5.4 Access Control Violation Fault
  - 5.5.5 Access Across A Page Boundary
  - 5.5.6 System Space Address Translation
  - 5.5.7 Process Space Address Translation
  - 5.5.8 P0 Region
  - 5.5.9 P1 Region
- 5.6 Translation Buffer
- 5.7 Faults and Parameters
- 5.8 Privileged Services and Argument Violation
  - 5.8.1 Changing Access Modes
  - 5.8.2 Validating Address Arguments (PROBE instructions)
  - 5.8.3 Notes On the PROBE instructions
Chapter 6 Exceptions and Interrupts
- 6.1 Introduction
  - 6.1.1 Process Interrupt Priority Levels (IPL)
  - 6.1.2 Interrupts
  - 6.1.3 Exceptions
  - 6.1.4 Contrast Between Exceptions and Interrupts
- 6.2 Processor Status
- 6.3 Interrupts
  - 6.3.1 Urgent Interrupts -- Levels 18-1F (Hex)
  - 6.3.2 Device Interrupts -- Levels 10-17 (Hex)
  - 6.3.3 Software Generated Interrupts -- Levels 01-0F (Hex)
    - 6.3.3.1 Software Interrupt Summary Register
    - 6.3.3.2 Software Interrupt Request Register
  - 6.3.4 Interrupt Priority Level Register
  - 6.3.5 Interrupt Example
- 6.4 Exceptions
  - 6.4.1 Arithmetic Traps/Faults
    - 6.4.1.1 Integer Overflow Trap
    - 6.4.1.2 Integer Divide By Zero Trap
    - 6.4.1.3 Floating Overflow Trap
    - 6.4.1.4 Divide By Zero Trap - Floating or Decimal String
    - 6.4.1.5 Floating Underflow Trap
    - 6.4.1.6 Decimal String Overflow Trap
    - 6.4.1.7 Subscript Range Trap
    - 6.4.1.8 Floating Overflow Fault
    - 6.4.1.9 Divide By Zero Floating Fault
    - 6.4.1.10 Floating Underflow Fault
  - 6.4.2 Memory Management Exceptions
    - 6.4.2.1 Access Control Violation Fault
    - 6.4.2.2 Translation Not Valid Fault
  - 6.4.3 Exceptions Detected During Operand Reference
    - 6.4.3.1 Reserved Addressing Mode Fault
    - 6.4.3.2 Reserved Operand Exception
  - 6.4.4 Exceptions Occurring as the Consequence of an Instruction
    - 6.4.4.1 Opcode Reserved To DIGITAL Fault
    - 6.4.4.2 Opcode Reserved to Customers (and CSS) Fault
    - 6.4.4.3 Compatibility Mode Exception
    - 6.4.4.4 Breakpoint Fault
  - 6.4.5 Tracing
    - 6.4.5.1 Trace Instruction Summary
    - 6.4.5.2 Using Trace
  - 6.4.6 Serious System Failures
    - 6.4.6.1 Kernel Stack Not Valid Abort
    - 6.4.6.2 Interrupt Stack Not Valid Halt
    - 6.4.6.3 Machine Check Exception
- 6.5 Serialization of Notification of Multiple Events
- 6.6 System Control Block (SCB)
  - 6.6.1 System Control Block Base (SCBB)
  - 6.6.2 Vectors
- 6.7 Stacks
  - 6.7.1 Stack Residency
  - 6.7.2 Stack Alignment
  - 6.7.3 Stack Status Bits
  - 6.7.4 Accessing Stack Registers
- 6.8 Initiate Exception or Interrupt
- 6.9 Related Instructions
- 6.10 Processor State Transition Table
Chapter 7 Process Structure
- 7.1 Process Definition
- 7.2 Process Context
  - 7.2.1 Process Control Block Base (PCBB)
  - 7.2.2 Process Control Block (PCB)
  - 7.2.3 Process Privileged Registers
- 7.3 Asynchronous System Traps (AST)
- 7.4 Process Structure Interrupts
- 7.5 Process Structure Instructions
- 7.6 Usage Example
Chapter 8 System Architectural Implications
- 8.1 Introduction
- 8.2 Data Sharing and Synchronization
- 8.3 Cache
- 8.4 Restartability
- 8.5 Interrupts
- 8.6 Errors
- 8.7 I/O Structure
  - 8.7.1 Introduction
  - 8.7.2 Constraints On I/O Registers
Chapter 9 Privileged Registers
- 9.1 Processor Register Space
- 9.2 Pre-Process Registers and Context Switching
- 9.3 Stack Pointer Images
- 9.4 MTPR and MFPR Instructions
- 9.5 VAX-11 Series Registers
  - 9.5.1 System Identification Register (SID)
  - 9.5.2 Console Terminal Registers
    - 9.5.2.1 VAX-11/780 Console Register Implementation
      - 9.5.2.1.1 Status Byte Definition
  - 9.5.3 Clock Registers
    - 9.5.3.1 Time-of-Year Clock
    - 9.5.3.2 Interval Clock
- 9.6 VAX-11/780 Specific Registers
  - 9.6.1 VAX-11/780 Accelerator
  - 9.6.2 VAX-11/780 Micro Control Store
  - 9.6.3 SBI Fault/Status Register (SBIFS)
  - 9.6.4 SBI Silo Data Register (SBIS)
  - 9.6.5 SBI Silo Comparator Register (SBISC)
  - 9.6.6 SBI Maintenance Register (SBIMT)
  - 9.6.7 SBI Error Register (SBIER)
  - 9.6.8 SBI Timeout Address (SBITA)
  - 9.6.9 SBI Quad Clear
- 9.7 VAX-11/750 Specific Registers
  - 9.7.1 CMI Error Register
  - 9.7.2 Console Storage Device Registers
  - 9.7.3 Translation Buffer Group Disable Register (TBDR)
  - 9.7.4 Cache Disable Register (CADR)
  - 9.7.5 Machine Check Error Summary Register (MCESR)
  - 9.7.6 Cache Error Register (CAER)
  - 9.7.7 Accelerator Control/Status Register
  - 9.7.8 Initialize UNIBUS (IORESET)
  - 9.7.9 Translation Buffer Data Register (TBDATA)
Chapter 10 PDP-11 Compatibility Mode
- 10.1 Introduction
- 10.2 Compatibility Mode User Environment
  - 10.2.1 General Registers and Addressing Modes
    - 10.2.1.1 Register Mode
    - 10.2.1.2 Register Deferred Mode
    - 10.2.1.3 Autoincrement Mode
    - 10.2.1.4 Autoincrement Deferred Mode
    - 10.2.1.5 Autodecrement Mode
    - 10.2.1.6 Autodecrement Deferred Mode
    - 10.2.1.7 Index Mode
    - 10.2.1.8 Index Deferred Mode
  - 10.2.2 The Stack
  - 10.2.3 Processor Status Word
  - 10.2.4 Instructions
    - 10.2.4.1 Single Operand Instructions
    - 10.2.4.2 Double Operand Instructions
    - 10.2.4.3 Branch Instructions
    - 10.2.4.4 Jump and Subroutine Instructions
    - 10.2.4.5 Return From Interrupts and Traps
    - 10.2.4.6 Miscellaneous
- 10.3 Entering and Leaving Compatibility Mode
  - 10.3.1 General Register Usage
- 10.4 Compatibility Mode Memory Management
- 10.5 Compatibility Mode Exceptions and Interrupts
  - 10.5.1 Reserved Instruction Fault
  - 10.5.2 BPT Instruction Fault
  - 10.5.3 IOT Instruction Fault
  - 10.5.4 EMT Instruction Fault
  - 10.5.5 TRAP Instruction Fault
  - 10.5.6 Illegal Instruction Fault
  - 10.5.7 Odd Address Error Abort
- 10.6 T Bit Operation in Compatibility Mode
- 10.7 Unimplemented PDP-11 Traps
- 10.8 Compatibility Mode I/O References
- 10.9 Processor Registers
- 10.10 Program Synchronization
Appendix A Instruction Set and Opcode Assignments
- A.1 Instruction Operand Formats
- A.2 Operand Specifier Notation
- A.3 Opcode Assignments
- A.4 Instructions Usable To Reference I/O Space

Company:	Digital Equipment Corporation
Part:	EK-VAXAR-RM-001 Revision 6.1
Date:	1982-05-20
Keywords:

Address:	http://bitsavers.org/pdf/dec/vax/archSpec/EK-VAXAR-RM-001_Arch_May82.pdf
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Address:	http://www.vaxhaven.com/images/7/78/EK-VAXAR-RM-001.pdf
Site:	VaxHaven
Format:	PDF
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VAX-11 Architecture Reference Manual

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