KA655 CPU Module Technical Manual

1 Overview
- 1.1 KA655 Central Processor Module
- 1.2 Clock Functions
- 1.3 Central Processing Unit
- 1.4 Floating-Point Accelerator
- 1.5 Cache Memory
- 1.6 Memory Controller
- 1.7 MicroVAX System Support Functions
- 1.8 Resident Firmware
- 1.9 Q22-bus Interface
- 1.10 MS650-BA Memory Modules
2 Installation and Configuration
- 2.1 Installing the KA655
- 2.2 Configuring the KA655
- 2.3 KA655 Connectors
  - 2.3.1 Console SLU Connector (J1)
  - 2.3.2 Configuration and Display Connector (J2)
  - 2.3.3 Memory Expansion Connector (J3)
- 2.4 H3600-SA CPU Cover Panel
- 2.5 KA630CNF Configuration Board
3 Architecture
- 3.1 Central Processor
  - 3.1.1 Processor State
    - 3.1.1.1 General Purpose Registers
    - 3.1.1.2 Processor Status Longword
    - 3.1.1.3 Internal Processor Registers
  - 3.1.2 Data Types
  - 3.1.3 Instruction Set
  - 3.1.4 Memory Management
    - 3.1.4.1 Translation Buffer
    - 3.1.4.2 Memory Management Control Registers
  - 3.1.5 Exceptions and Interrupts
    - 3.1.5.1 Interrupts
    - 3.1.5.2 Exceptions
    - 3.1.5.3 Information Saved on a Machine Check Exception
    - 3.1.5.4 System Control Block
    - 3.1.5.5 Hardware Detected Errors
    - 3.1.5.6 Hardware Halt Procedure
  - 3.1.6 System Identification
  - 3.1.7 CPU References
    - 3.1.7.1 Instruction-Stream Read References
    - 3.1.7.2 Data-Stream Read References
    - 3.1.7.3 Write References
- 3.2 Floating-Point Accelerator
  - 3.2.1 Floating-Point Accelerator Instructions
  - 3.2.2 Floating-Point Accelerator Data Types
- 3.3 Cache Memory
  - 3.3.1 Cacheable References
  - 3.3.2 First-Level Cache
    - 3.3.2.1 First-Level Cache Organization
    - 3.3.2.2 First-Level Cache Address Translation
    - 3.3.2.3 First-Level Cache Data Block Allocation
    - 3.3.2.4 First-Level Cache Behavior on Writes
    - 3.3.2.5 Cache Disable Register
    - 3.3.2.6 Memory System Error Register
    - 3.3.2.7 First-Level Cache Error Detection
  - 3.3.3 Second-Level Cache
    - 3.3.3.1 Second-Level Cache Organization
    - 3.3.3.2 Second-Level Cache Address Translation
    - 3.3.3.3 Second-Level Cache Data Block Allocation
    - 3.3.3.4 Second-Level Cache Behavior on Writes
    - 3.3.3.5 Cache Control Register
    - 3.3.3.6 Second-Level Cache Error Detection
    - 3.3.3.7 Second-Level Cache as Fast Memory
- 3.4 Main Memory System
  - 3.4.1 Main Memory Organization
  - 3.4.2 Main Memory Addressing
  - 3.4.3 Main Memory Behavior on Writes
  - 3.4.4 Main Memory Error Status Register
  - 3.4.5 Main Memory Control and Diagnostic Status Register
  - 3.4.6 Main Memory Error Detection and Correction
- 3.5 Console Serial Line
  - 3.5.1 Console Registers
    - 3.5.1.1 Console Receiver Control/Status Register
    - 3.5.1.2 Console Receiver Data Buffer
    - 3.5.1.3 Console Transmitter Control/Status Register
    - 3.5.1.4 Console Transmitter Data Buffer
  - 3.5.2 Break Response
  - 3.5.3 Baud Rate
  - 3.5.4 Console Interrupt Specifications
- 3.6 Time-of-Year Clock and Timers
  - 3.6.1 Time-of-Year Clock
  - 3.6.2 Interval Timer
  - 3.6.3 Programmable Timers
    - 3.6.3.1 Timer Control Registers
    - 3.6.3.2 Timer Interval Registers
    - 3.6.3.3 Timer Next Interval Registers
    - 3.6.3.4 Timer Interrupt Vector Registers
- 3.7 Boot and Diagnostic Facility
  - 3.7.1 Boot and Diagnostic Register
  - 3.7.2 Diagnostic LED Register
  - 3.7.3 ROM Memory
    - 3.7.3.1 ROM Socket
    - 3.7.3.2 ROM Address Space
    - 3.7.3.3 Resident Firmware Operation
  - 3.7.4 Battery Backed-Up RAM
  - 3.7.5 KA655 Initialization
    - 3.7.5.1 Power-Up Initialization
    - 3.7.5.2 Hardware Reset
    - 3.7.5.3 I/O Bus Initialization
    - 3.7.5.4 I/O Bus Reset Register
    - 3.7.5.5 Processor Initialization
- 3.8 Q22-bus Interface
  - 3.8.1 Q22-bus to Main Memory Address Translation
    - 3.8.1.1 Q22-bus Map Registers
    - 3.8.1.2 Accessing the Q22-bus Map Registers
    - 3.8.1.3 Q22-bus Map Cache
  - 3.8.2 CDAL Bus to Q22-bus Address Translation
  - 3.8.3 Interprocessor Communication Register
  - 3.8.4 Q22-bus Interrupt Handling
  - 3.8.5 Configuring the Q22-bus Map
    - 3.8.5.1 Q22-bus Map Base Address Register
  - 3.8.6 System Configuration Register
  - 3.8.7 DMA System Error Register
  - 3.8.8 Q22-bus Error Address Register
  - 3.8.9 DMA Error Address Register
  - 3.8.10 Error Handling
4 KA655 Firmware
- 4.1 KA655 Firmware Features
  - 4.1.1 Halt Entry, Exit, and Dispatch
    - 4.1.1.1 Halt Entry -- Saving Processor State
    - 4.1.1.2 Halt Exit -- Restoring Processor State
    - 4.1.1.3 Halt Dispatch
    - 4.1.1.4 External Halts
  - 4.1.2 Power-Up
    - 4.1.2.1 Initial Power-Up Test
    - 4.1.2.2 Locating a Console Device
  - 4.1.3 Mode Switch Set to Test
  - 4.1.4 Mode Switch Set to Query
  - 4.1.5 Mode Switch Set to Normal
  - 4.1.6 LED Codes
- 4.2 Console Service
  - 4.2.1 Console Control Characters
  - 4.2.2 Console Command Syntax
  - 4.2.3 Console Command Keywords
  - 4.2.4 Console Command Qualifiers
  - 4.2.5 Console Address Specifiers
  - 4.2.6 References to Processor Registers and Memory
  - 4.2.7 Console Commands
    - 4.2.7.1 BOOT
    - 4.2.7.2 CONFIGURE
    - 4.2.7.3 CONTINUE
    - 4.2.7.4 DEPOSIT
    - 4.2.7.5 EXAMINE
    - 4.2.7.6 FIND
    - 4.2.7.7 HALT
    - 4.2.7.8 HELP
    - 4.2.7.9 INITIALIZE
    - 4.2.7.10 MOVE
    - 4.2.7.11 NEXT
    - 4.2.7.12 REPEAT
    - 4.2.7.13 SEARCH
    - 4.2.7.14 SET
    - 4.2.7.15 SHOW
    - 4.2.7.16 START
    - 4.2.7.17 TEST
    - 4.2.7.18 UNJAM
    - 4.2.7.19 X -- Binary Load and Unload
    - 4.2.7.20 ! -- Comment
  - 4.2.8 Conventions for Tables 4-5 and 4-6
- 4.3 Bootstrapping
  - 4.3.1 Boot Devices
  - 4.3.2 Boot Flags
  - 4.3.3 Preparing for the Bootstrap
  - 4.3.4 Primary Bootstrap, VMB
  - 4.3.5 Device-Dependent Bootstrap Procedures
    - 4.3.5.1 Disk and Tape Bootstrap Procedure
    - 4.3.5.2 PROM Bootstrap Procedure
    - 4.3.5.3 Network Bootstrap Procedure
    - 4.3.5.4 Network Listening
- 4.4 Diagnostics
  - 4.4.1 Error Reporting
  - 4.4.2 Diagnostic Interdependencies
  - 4.4.3 Areas not Covered
- 4.5 Operating System Restart
  - 4.5.1 Locating the RPB
- 4.6 Machine State on Power-Up
  - 4.6.1 Main Memory Layout and State
    - 4.6.1.1 Reserved Main Memory
    - 4.6.1.2 PFN Bitmap
    - 4.6.1.3 Scatter/Gather Map
    - 4.6.1.4 Contents of Main Memory
  - 4.6.2 CMCTL Registers
  - 4.6.3 First Level Cache
  - 4.6.4 Translation Buffer
  - 4.6.5 Second Level Cache
  - 4.6.6 Halt Protected Space
- 4.7 Public Data Structures and Entry Points
  - 4.7.1 Firmware EPROM Layout
  - 4.7.2 Call-Back Entry Points
    - 4.7.2.1 CP$GETCHAR_R4
    - 4.7.2.2 CP$MSG_OUT_NOLF_R4
    - 4.7.2.3 CP$READ_WITH_PRMPT_R4
  - 4.7.3 SSC RAM Layout
    - 4.7.3.1 Public Data Structures
    - 4.7.3.2 Firmware Stack
    - 4.7.3.3 Diagnostic State
    - 4.7.3.4 USER Area
- 4.8 Error Messages
  - 4.8.1 Halt Code Messages
  - 4.8.2 Console Error Messages
  - 4.8.3 VMB Error Messages
A KA655 Specifications
- A.1 Physical Specifications
- A.2 Electrical Specifications
- A.3 Environmental Specifications
B Address Assignments
- B.1 General Local Address Space Map
- B.2 Detailed Local Address Space Map
- B.3 External IPRs
- B.4 Global Q22-bus Address Space Map
C Q22-bus Specification
- C.1 Introduction
  - C.1.1 Master/Slave Relationship
- C.2 Q22-bus Signal Assignments
- C.3 Data Transfer Bus Cycles
  - C.3.1 Bus Cycle Protocol
  - C.3.2 Device Addressing
- C.4 Direct Memory Access
  - C.4.1 DMA Protocol
  - C.4.2 Block Mode DMA
    - C.4.2.1 DATBI Bus Cycle
    - C.4.2.2 DATBO Bus Cycle
  - C.4.3 DMA Guidelines
- C.5 Interrupts
  - C.5.1 Device Priority
  - C.5.2 Interrupt Protocol
  - C.5.3 Q22-bus Four-Level Interrupt Configurations
- C.6 Control Functions
  - C.6.1 Memory Refresh
  - C.6.2 Halt
  - C.6.3 Initialization
  - C.6.4 Power Status
  - C.6.5 BDCOK H
  - C.6.6 BPOK H
  - C.6.7 Power-Up and Power-Down Protocol
- C.7 Q22-bus Electrical Characteristics
  - C.7.1 Signal Level Specifications
  - C.7.2 Load Definition
  - C.7.3 120-Ohn Q22-bus
  - C.7.4 Bus Drivers
  - C.7.5 Bus Receivers
  - C.7.6 Bus Termination
  - C.7.7 Bus Interconnecting Wiring
    - C.7.7.1 Backplane Wiring
    - C.7.7.2 Intrabackplane Bus Wiring
    - C.7.7.3 Power and Ground
- C.8 System Configurations
  - C.8.1 Power Supply Loading
- C.9 Module Contact Finger Identification
D Acronyms

Company:	Digital Equipment Corporation
Part:	EK-KA655-TM-001
Date:	1989-01
Keywords:	MicroVAX 3900

Address:	https://vt100.net/dec/ek-ka655-tm-001.pdf
Site:	VT100.net
Format:	PDF
Size:	13896318 bytes (13.3 MiB)

Address:	http://bitsavers.org/pdf/dec/vax/655/EK-KA655-TM-001_KA655_CPU_Module_Technical_Manual_Jan89.pdf
Site:	Al Kossow's Bitsavers
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KA655 CPU Module Technical Manual

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